ASIC Design Flow Using Synthesis

The synthesis based ASIC design flow includes the following steps  

---

We empirically validate proposed transformations and the entire RUMBLE flow. We show how these techniques can be used to significantly improve initial latch placement in a reasonably optimized ASIC design. Our do-no-harm acceptance criteria reject solutions if any quality metrics are degraded. This key feature facilitates the use of RUMBLE later in physical synthesis. 

---