Wafered aspect

Microfabrication processes have been used successfully to form micro-fuel cells on silicon wafers. Aspects of the design, materials, and forming of a micro-fabricated methanol fuel cell have been presented. The processes yielded reproducible, controlled structures that performed well for liquid feed, direct methanol/Oj saturated solution (1.4 mW cm ) and direct methanol/H O systems (8 mA cm" ). In addition to optimizing micro-fuel cell operating performance, there are many system-level issues to be considered when developing a complete micro power system. These issues include electro-deposition procedure, catalyst loading, channel depth, oxidants supply, and system integration. The micro-fabrication processes that have... 

Figure 2,108 Piezoelectric quartz crystal with vacuum-deposited electrodes. Gold is deposited on both sides of the quartz wafer a in the pattern shown. Electrical connection is made to the electrode flag b by means of a spring clip with attached lead c. The circular gold electrode in the crystal centre d opposes an identical electrode on the other side of the crystal. Electrical connection to the opposing electrode is made to the electrode flag e. Reprinted from Electrochimica Acta, 30, S. Bruckenstein and M. Shay, Experimental aspects of use of the quartz crystal micrnhalance in solution, pp. 1295-1.100 (1985), with kind permission from Pergamon Press Ltd., Headington Hill Hall, Oxford 0X3 0BW, UK.

To treat all the different wet processes for silicon wafers developed in the last five decades exhaustively would make up a book of its own. However, a few basic aspects are important, because chemical etching of silicon is closely related to the electrochemical behavior of Si electrodes, especially to the OCP condition. A brief overview of the most common etching and cleaning solutions will be given, with emphasis on the electrochemical aspects. 

The three-dimensional circuit elements are fabricated by a series of processes collectively known as lithography . The pattern is first generated in a polymeric film on a device wafer and this pattern is then transferred via etching, into the underlying thin film. The purpose of this book is to review the theory, materials, and processes that are used in the lithographic process. This book is intended to be a tutorial and not a comprehensive review. Each chapter contains many references to which the reader can refer for more detail on any specific aspect of microlithography. 

The square or pseudo-square blocks are cut into thin wafers using multi-wire saws, a technique which was developed specifically for PV and which is now common in the semiconductor industry also. A great deal of progress has been made with equipment and process control aspects and in introducing reduced diameter wires several hundred kilometers long for reduced kerf loss. 

The cost per CMP wafer pass is high when compared to other semiconductor manufacturing processes. This aspect of CMP reflects the rapid transfer of CMP into production, as well as the large amount of slurry and pads that are consumed during CMP. CMP CoO has improved in the last few years due to several factors. 

As understanding of the CMP process improves, one can expect a great deal of work in all aspects of CMP modeling and simulation. These improvements are likely to extend over many length scales spanning wafer-level polish and uniformity concerns to die-level prediction to microscopic feature, chemical, and mechanical interactions. 

Very little will be said here concerning the equipment aspects of plasma etching. There are three basic types of equipment which have been used a) barrel systems, b) planar systems, and c) systems in which the wafers are located downstream from the plasma to be referred to in this paper as downstream etching systems. These plasma etching configurations are shown schematically in Fig. 3.1. Often the barrel systems are used with a perforated metal tube called an etch tunnel which is shown in Fig. 3.1 a and b. The purpose of the etch tunnel is to protect the wafers from the energetic ion and electron bombardment to which waters immersed directly... 

Thus, if T < 1, the deposition proceeds more rapidly at the wafer edge than at the interior of the wafer, and a nonuniform film thickness results. This result is the so-called bull s-eye effect. Figure 15a illustrates the variation in i] with < ) for a first-order reaction and a large aspect ratio, A = RJA. For the first-order reaction, the film thickness has the well-known form... 

Fig. 48. The surface patter of Si02 stripes on a silicon wafer was prepared electrochemically by applying a bias pulse to locally remove the terminal hydrogen atoms. The aspect ratio (height/width) of oxide lines improves significantly when the relative humidity is lowered from 61% to 14%. Reproduced from [445]...

Photoablation (diode-pumped Nd YV04 laser, X = 532 nm) was used to create a master on the PMMA layer coated on a Si wafer (see Figure 2.20a). The PMMA layer was doped with rhodamine B to facilitate the absorption of the laser radiation. The width of the ablated features depends on the diameter and the position of the laser focal point. The best aspect ratios were obtained with the laser beam focused 3 1 pm into the PMMA film. The ablated PMMA-Si master was used to cast a PDMS layer (see Figure 2.19b). The cast PDMS layer appeared to have smoother surfaces than the PMMA master [367]. 

On-wafer membrane deposition and patterning is an important aspect of the fabrication of planar, silicon based (bio)chemical sensors. Three examples are presented in this paper amperometric glucose and free chlorine sensors and a potentiometric ISRET based calcium sensitive device. For the membrane modified ISFET, photolithographic definition of both inner hydrogel-type membrane (polyHEMA) and outer siloxane-based ion sensitive membrane, of total thickness of 80 pm, has been performed. An identical approach has been used for the polyHEMA deposition on the free chlorine sensor. On the other hand, the enzymatic membrane deposition for a glucose electrode has been performed by either a lift-off technique or by an on-chip casting. 

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