Unwanted latches

Ensure that all signals are initialized. Further, when using case statements or nested if statements, ensure that they are fully defmed. A full specification will prevent latches from being inferred. 

Consider the Example 2.2 shown above. Notice that the expected result when dk is not equal to T is not specified. DC interprets this to mean that when clk=l condition is not satisfied, retain the previous value of q. Hence, latches are inferred. After reading in the HDL, one does not have to compile the design to realize that unwanted latches have been inferred. The dc shell output provides information on memory devices inferred as shown below  

Statistics for inferred devices in process at line 15 in file /home/testvhd 

IVariade State Devices Width Conditionally Driven (Line ) 7 

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The best way to avoid latches is to first determine from the synthesis tool how many latches have been inferred. A designer now needs to go back and check if each latch inferred really needs to be a latch. It could be that the designer never intended for a latch or the designer forgot to specify values under all conditions. The best rale is to check the latches that get synthesized and go back and determine why each latch got synthesized and fix code if necessary to avoid any unwanted latches. 

In this section, we discuss some basic issues related to HDL coding for synthesis such as VHDL types, unwanted latches, variables and signals, and priority encoding. For a certain desired functionality, it is often possible to code HDL in a number of different ways. However, there are several guidelines that one can follow to develop a consistent coding style for synthesis. 

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