Trench etching

Fig. 8.9. Stress fields at the end of a trench etched in a 15f

With this optimization technique, topography is reduced after the planarization step. The STI trenches are filled with polysilicon instead of Si02 [39]. After trench, etching, the first patterned hard mask is stripped and a new continuous oxide/nitride layer is deposited for electrical isolation between the substrate and the trench polysilicon. After CMP, the dishing in isolation areas is counteracted by a high-temperature oxidation step, which oxidizes the upper part of the remaining polysilicon in the trenches. As the volume of the Si02 is... 

Factors evaluated in this program include slurry selectivity, polish time, trench etch, film deposition, and dummy structure. Finally, plysical and electrical data are correlated to determine if the process window is robust enough for volume production. 

The authors would like to thank the personnel in the Silicon Facility at TOSHIBA TAMAGAWA for processing the wafers. Special thanks go to S.Kikuchi and M.Terasaki for the lithography, K.doi for the trench fill, Y.Otani for the trench etching, and K.lwade for the line process. And authors gratefolly acknowledge H.Kato, Tokuyama research Lab. for usefol experimental support. 

H. Jansen, M. de Boer, R. Lengten-bergh, M. Elwenspoek, The black silicon method a universal method for determining the parameter setting of a fluorine-based reactive ion etcher in deep silicon trench etching with profile control, Proc. Micromechanics Europe 1994, 60-64. 

Next, the sacrificial layer is patterned and holes are etched into the oxide using established lithography and etching processes. These holes will be filled and thus act as anchor points on the left end of the two cantilevers formed later (Fig. 5.3.1 e). In the next step, the functional polysilicon layer is deposited (Fig. 5.3.1b). The thickness of this layer determines the mechanical properties of the movable beam. The thicker it is, the stiffer the beam will be in the z axis, which is desirable for structures intended to move only in the xy direction. But its thickness is limited by the capabilities of the deposition process used. The functional layer is next patterned and etched (Fig. 5.3.1c). Depending on the thickness of the polysilicon layer, specific trench etch processes (as described later on) may be required, especially when this layer is rather thick. Finally, the sacrificial layer is removed (Fig. 5.3.1 d). This is typically done with wet or vapor phase etches to dissolve the silicon dioxide and leave parts of the functional structures free-standing and movable. When using wet etching, special care has to be taken to prevent Stic-... 

The epi-polysilicon functional layer is patterned and then etched by the trench etch process described in Section 5.3.4.2. The trench etching forms cantilever beams that act as comb fingers in the acceleration sensor, as well as the insulating trench required for electrical separation of the epipolysilicon wiring and bond pad structures (Fig. 5.3.11 e). Straight, unnotched sidewalls are strictly required, especially for all design elements that form springs or capacitive comb structures. 

The main trench etch patterning issues include pattern distortion, proximity, and microloading effects. Figure 13.48 shows cross-sectional SEM images of a 160-nm trench patterned into Si02 substrate with an acrylate resist, showing smooth feature sidewalls. 

Figure 16.7 Process sequence for STI trench etch (a) cleaning of the wafer, (b) barrier oxide deposition, (c) nitride deposition, (d)STI lithographic masking (involving mask 3) to define isoiation region, and (e) seiective opening of isolation areas in the epitaxial layer by the STI trench etch. Then the wafer is stripped of resist and finally, cleaned.

Jansen H, de Boer M, Wiegerink R, Tas N, Smulders E, Neagu C, Elwenspoek M (1997) RIE lag in high aspect ratio trench etching of silicon. Microelectron Eng 35 45—50... 

Silicon Micromachining, Fig. 11 Scanning electron microscope (SEM) photograph illustrating high aspect ratio and vertical silicon trenches etched by DRIB... 

Figure 4.8 ULK films with higher interconnected porosity typically suffer from higher plasma-induced damage during trench etch. This damaged layer is more readily etched in dilute hydrofluoric acid (Reprinted with permission from Gates et al., 2009a).

The compensation structures of the super junction device are realized by a deep trench etch (depth 10—25 pm, width 2—4 pm) before trench-gate definition, followed by a Si epitaxial trench fill (p-doped) and CMP of the Si layer. If no polish stop layer is introduced, the pohshing has to be performed in a time-controlled manner. With a stop layer, a high-selectivity Si slurry has to be used, while in the latter case a nonselective slurry is required. Figure 18.7(a—c) show etched trenches (a), epitaxially filled with p-doped Si (b) and time-controlled polish with a Si slurry (c). 

Figure 18.7 Fabrication of the compensation structures of super junction power MOSFETs. Trench etch (a), epitaxially filled with p-doped Si (h) and after time-controlled Si CMP (c).

Chakravarty D, Sarada BV, Chandrasekhar SB, Saravanan K, Rao TN (2011) A novel method of fabricating porous silicon. Mater Sci Eng A 528 7831-7834 Christophersen M, Merz P, Quenzer J, Carstensen J, Foil H (2001) Deep electrochemical trench etching with organic hydrofluoric electrolytes. Sens Actuator A 88 241-246 Coblenz WS (1990) The physics and chemistry of the sintering of silicon. J Mater Sci 25 2754-2764 De Castro CL, Mitchell BS (2002) Nanoparticles from mechanical attrition. In Baraton M-I (ed) Synthesis, functionalization and surface treatment of nanoparticles. American Scientific Publisher, Stevenson Ranch... 

The silicon device layer is metallized with gold (500 nm Au/20 nm Cr) and patterned with the PAD METAL mask using a photolithographic lift-off process that is capable of defining 3 pm lines and spaces with a 3 pm alignment tolerance. This metal layer is exposed to high temperatures during the subsequent process steps, so it does not provide an optical quality surface for mirrors like the second metallization that is patterned with the BLANKET METAL mask. Any metal features that are defined in the first metal deposition will be in electrical contact unless they are separated by a trench etched in the device layer since the surface of the device layer is heavily doped with phosphorus. 

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