Top contact/bottom gate

TC/BG BC/BG SC/BG BC/TG PR-TRMC Top contact/bottom gate Bottom contact/bottom gate Sandwich contact/bottom gate Bottom contact/top gate Pulse-radiolysis time-resolved microwave conductivity technique... 

Fig. 1 Schematic drawing of the structures of four kinds of typical OFET devices (a) Top contact/bottom gate (TC/BG) (b) Top view of (a), W channel width, L channel length (c) bottom contact/bottom gate (BC/BG) (d) sandwich contact/bottom gate (SC/BG) and (e) bottom contact/top gate (BC/TG)...

Fig. 4. Schematic of top-contact/bottom-gate OFET device and structures of the CPB precursors (polymer and silane crosslinkers) employed in this study.

The different transistor geometries can strongly influence the device performance. The most commonly used configurations are top contact/bottom gate (TC/BG),... 

TOP-CONTACT, BOTTOM-GATE BOTTOM-CONTACT, BOTTOM-GATE... 

Fig. 17.2 (a) Top-contact, bottom-gate device (b) bottom-contact, bottom-gate device (c) bottom-contact, top-gate device (d) working mechanism of a FET device with p-type materials (e) transfer characteristic curve of FET device and (f) output characteristic curve of FET device... 

Cross sections of schematic top and bottom gate TFTs are illustrated in Figure 24.1. They consist of a thin semiconducting film, ideally forming ohmic contacts to the soiuce and drain electrodes. In addition, the semiconductor is separated by an insulating layer from the gate electrode. 

Fig. 1 Molecular structure of regioregular P3HT (ir-P3HT) and different transistor geometries (a) bottom contact/top gate, (b) top contact/bottran gate, and (c) bottom contact/bottom gate, (d) Structure and working principle of electrolyte-gated, electrochemical transistors...

Fig. 1.3. Schematic view of the structure of organic thin film transistors. Both structures are top-gated, (a) Bottom contact (BC) (b) Top contact (TC).

Bottom-gate, top-contact (Fig. 4.2a) and a bottom-gate, bottom-contact (Fig. 4.2b) TFT configurations are used to evaluate the FET performance of our semiconductors. The devices are built on an n-doped silicon wafer (gate electrode) with a 100-nm thermal silicon oxide (SiC>2) dielectric layer which is modified with a self-assembled monolayer of octyltrichlorosilane (OTS-8) to promote molecular ordering in the semiconductor layer. For the top-contact device the semiconductor layer ( 20-50 nm) is deposited on the OTS-8-modified SiC>2 surface by spin coating. A... 

Fig. 4.2. Schematic diagrams of bottom-gate, top-contact (a) and bottom-gate, bottom-contact (b) thin film transistor test configurations.

Mottaghi and Horowitz [164] have investigated the degradation of carrier mobility in pentacene TFTs due to effect of electric field. They fabricated pentacene-based OTFTs with bottom-gate, top-contact architecture. Alumina was used as substrate. In one set of devices pentacene was deposited directly on alumina. In the second set of devices a fatty... 

Figure 17.2 (a) Chemical structures of the used materials fullerene (Ceo) and copper-phthalocyanine (CuPc). Top view (b) and cross section (d) of the ring-type transistor in bottom-gate and bottom-contact geometry. Top view (c) and cross section (d) of the ring-type inverter. The silicon substrate acts as the gate electrode for transistors and inverters. 

The most simple pentaeene OTFT test structure used in many labs is based on a Si wafer piece covered with a thermal oxide. Here, the heavily doped Si wafer takes the role of the back gate electrode, and the Si02 takes the role of the gate dielectric. A pentacene thin film is deposited as the semiconducting layer. Source and drain electrodes are deposited either on the silicon oxide (bottom contact) or on top of the pentacene film (top contact). 

Beeause of the high euring temperature of the introdueed polyimide film, it is inapplieable to polymer substrates. Therefore, a eommereially available eoating varnish Beetron (based on modified alkyd ehemistry), favoured beeause of the low euring temperature of about 80 °C, is spin eoated onto a silieon substrate. It is eured in a eonveetion oven at 80 °C for 30 min, resulting in a 1 pm to 1.5 pm thiek film. In eontrast to the OFETs mentioned in this ehapter so far, the transistor on the Beetron varnish uses bottom gate and titanium top drain and source contacts, structured by a shadow mask. The latter is due to the lack of chemical resistance of the varnish towards solvents. 

Section 20.2 presents the sample geometries and preparation techniques, and Sections 20.3 and 20.4 summarise oiu findings for bottom and top contact geometries, respectively. In the latter case, we compare gate oxides with and without application of an OTS self-assembled monolayer. The main achievements of the present work are summarised in Section 20.5. 

There are two main architectnres to choose from in OFET fabrication the top contact and the bottom contact conhgurations. The physical difference between the two is the order of fabrication steps. That is, the source/drain contacts are either deposited before or after the semiconductor layer is deposited to create a bottom contact or top contact device, respectively. One can also bnild the entire transistor on top of the semicondnctor layer (the so-called top gate architectures), in which the insulator... 

FIGURE 2.4.7 Four possible OFET architectures (in cross-section), including (a) top contacts, (b) bottom contacts, (c) top contacts with a top gate, and (d) bottom contacts with a... 

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