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Source and drain contacts

One of the critical operating junctions in OFET devices is the source and drain contact to the channel. Any barrier between the contacts and the channel will appear in series and impede the flow of charge through the device. The source and drain electrode formation and structure can also influence the properties of the transistor channel itself. Crystal growth nucleated on the source and drain and the processes used to pattern the source and drain electrodes can have a significant effect on overall device performance. [Pg.57]


Fig. 3 Pentacene grown by supersonic molecular beam deposition to form near monolayer p-type FETs with thiolate monolayer modified Au source and drain contacts (a) visualized by atomic force microscopy and with well-behaved (b) /d-Eds and (c) -Eg characteristics... Fig. 3 Pentacene grown by supersonic molecular beam deposition to form near monolayer p-type FETs with thiolate monolayer modified Au source and drain contacts (a) visualized by atomic force microscopy and with well-behaved (b) /d-Eds and (c) -Eg characteristics...
Electrostatic bonding of the crystal on top of a previously prepared gate-insulator-source-drain structure [92-94]. Sometimes the source and drain contacts have been deposited afterwards, on top of the crystal [90]. [Pg.26]

The n+ underlay was used with the source and drain contacts to provide good electron-injecting properties. This caused the reproducibility of the contacts to increase, and the ON current obtained in this way increased significantly. For example, devices with n+ contacts consistently produced source-drain currents a factor of about three higher than the best currents obtained without the n+ layers. [Pg.95]

Values of determined by both the above methods agree to within 10% or better and, at room temperature, were typically 0.2-0.3 cm2 V-1 sec-1 in magnitude. The sample represented in Fig. 12 has a room-temperature mobility of 0.31 cm2 V-1 sec-1 with an activation energy EM of 0.11 eV. Figure 13 shows versus 103/T curves for three devices measured under these conditions, and Fig. 14 summarizes the values of EM as a function of Vc. Curve a in Fig. 14 represents data from earlier samples that did not employ n+ contacts at the source and drain contacts. Curve c represents data from the latest optimized FETs and curve b an intermediate stage in this development. At zero gate voltage, all three curves lead to values of—0.7... [Pg.103]

Figure 16 shows the transfer characteristics of some typical a-Si H FETs used in the experiments, both before and after irradiation. The postirradiation curves have been shifted by the amount of their AVr (stated for each curve) to facilitate the comparison and show clearly the changes produced by the irradiation. It is evident that no major deterioration in performance has occurred in fact, the decrease in transconductance was less than 10% in all cases. When the above-mentioned samples were annealed at 130 °C, with their gate, source, and drain contacts connected together, the FETs returned to their original transfer characteristics and threshold voltages. [Pg.107]

Fig. 7. (Top) Schematic layout of the TFT in the addressing matrix. Cross-hatched area is the drain pad and the dotted area is the source contact. The gap between the source and drain contact is bridged by the underlying gate electrode (broken line) and the a-Si H semiconductor (not shown). (Bottom) View of the finished matrix. The small dark strip is a-Si H. The bright central square is the drain pad, doubling as the optical reflector of the guest-host display. Note that the transistor completely surrounds the drain pad. Fig. 7. (Top) Schematic layout of the TFT in the addressing matrix. Cross-hatched area is the drain pad and the dotted area is the source contact. The gap between the source and drain contact is bridged by the underlying gate electrode (broken line) and the a-Si H semiconductor (not shown). (Bottom) View of the finished matrix. The small dark strip is a-Si H. The bright central square is the drain pad, doubling as the optical reflector of the guest-host display. Note that the transistor completely surrounds the drain pad.
Figure 4.18. Cross-section schematic of an advanced transistor design. Features illustrated are (a) raised source and drain contacts, (b) an SOI substrate that prevents off-state leakage from source to drain, and (c) a high-K dielectric gate insulator. These three components employed in tandem are the basis of a faster generation of transistors referred to as terahertz transistors. ]... Figure 4.18. Cross-section schematic of an advanced transistor design. Features illustrated are (a) raised source and drain contacts, (b) an SOI substrate that prevents off-state leakage from source to drain, and (c) a high-K dielectric gate insulator. These three components employed in tandem are the basis of a faster generation of transistors referred to as terahertz transistors. ]...
Source and drain contacts were deposited on top of the Pc films by thermal evaporation of Au (purity 99.99%) through shadow masks. The layout of the shadow mask yielded 8 independent OFETs on one sample. Samples are noted as A to F in the following, and distinct OFETs are noted as Al, A2, etc. [Pg.141]

The source and drain contacts of the examined OFETs were deposited by thermal evaporation of Au as described above for deposition of the radiotracers. Deposition of the contacts was not performed in the same chamber as the radio-tracer deposition in order to avoid contamination of the sample with radioactive isotopes. Patterning of the contact stractures was obtained using a stainless steel shadow mask. By deposition of Au an array of nine contacts was formed. The contact area of the Au was 50 x 50 pm and the distance between the contacts varied from 300 pm to 3290 pm. Three Au contact arrays with a thickness of 50 nm were deposited onto a 40 nm Pc film at a substrate temperature of 75 °C. The first contact array (Array 1 in the following) was deposited at a rate of 0.8 nm/min. For the second set of contacts (Array 2 in the following) first a submonolayer of Au was deposited very slowly (< 1 ML/h) on top of the Pc film in order to allow strong diffusion. Afterwards, the contacts were deposited at the same rate of 0.8 nm/min as the first set. The third array (Array 3 in the following) was deposited at 0.8 nm/min with the substrate at room temperature. [Pg.403]


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