The 2.5-D Implementation

According to the analysis presented in the previous section, we realized that the most effective way to reduce critical path delay is to fold the fabric into two stacked chips under the 2.5-D scenario. Therefore, we vertically split the chip into two halves and the resultant two chips can be bonded in a face-to-face manner. The layouts of the two chips in 2.5-D system are shown in Fig. 3.9. Note that the size 

All the pads are placed on the bottom level chip. Since the bottom chip has a smaller footprint than the original design does, the distance between pads is uniformly scaled down so that the pads can be fitted to the short perimeter. 

In the original monolithic design, the reconfigurable fabric is surrounded by a 

In the new design, we use two H-trees to deliver clock signals for the top level chip and bottom level chip, respectively. The two H-trees are interconnected through 128 inter-chip contacts to reduce clock skew. 

Finally, we need 900 inter-chip contacts for power distribution so make sure (1) current density of a 1-micron thick A1 power wire should be within 0.4 mA/ micron to 1 mA/micron[13] (2) current density of an inter-chip contact should be under 0.1 mA/micron[13]. According to our calculation, the worst-case IR dropping is within 9.6 mV. 

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Figure 2.2 Silicon area of the 2.5-D implementation with 4 slices of chips...

D ASIC Physical Design Automation For ASIC designs, it s not feasible to find an optimized 2.5-D implementation manually. Therefore, we have to build the first-generation 2.5-D layout design tools to automatically implement stacked layout. Then we can compare the interconnect characteristics between the monolithic and 2.5-D layout implementations of a give system and thus assess the feasibility of the 2.5-D paradigm. 

In a flattened design style, layout designers directly cany out the 2.5-D placement and routing tasks on a flatten netlist consisting of both standard cells and macros. Such a flow could usually accomplish superior solution quality, but at the cost of a longer turnaround time because of the inability to implement different blocks in parallel. 

In the time frame of 10 years, we believe the 2.5-D integration will enable the VLSI systems to achieve superior performance that is impossible for their monolithic implementations. In this section we discuss two such examples. 

In our 2.5-D layout design framework, we constructed a global router that could handle both monolithic and 2.5-D design implementations. After the floorplan design... 

A Series of 2.5-D Physical Design Tools Due to the complexity of modem ASIC designs, automatic EDA tools are critical for a successful layout implementation. For 2.5-D integrated ASIC systems, additional complexity is introduced by the large amount of inter-chip communication resource. To be able to pack an ASIC system in a 2.5-D space, we developed 2.5-D floorplanning, placement and... 

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