Surface mounting technology packages

QUADPACK Generic term for surface mount technology packages with leads on aU four sides. 

Surface Mount Technology (SMT), A Compendum of Technical Articles Presented at the First, Second, and Third Annual Conferences International Electronics Packaging Society Glen Ellyn, IL, 1984. 

Hutchins, C.L. Nov. 1994. Understanding grid array packages. SMT Surface Mount Technology.) Hutchins and Associates, Raleigh, NC. 

In surface mount technology, the components are soldered directly to the surface of a PWB, as opposed to thro ugh-hole mounting. This allows efficient use of board real estate, resulting in smaller boards and simpler assembly. Significant improvement in electrical performance is possible with the reduced package parasitics and the short interconnections. However, the reliability of the solder joint is a concern if there are CTE mismatches (Seraphim et al, 1989). 

Hollomon, J.K., Jr. 1995. Surface Mount Technology for PC Board Design. Prompt, Indianapolis, IN. Holmes, J.G. 1993. Surface mount solution for power devices. Surface Mount Technology 7(9) 18-20. Hwang, J.S. 1989. Solder Paste in Electronics Packaging. Van Nostrand Reinhold, New York. 

Mims, F.M., III. 1987. Surface mount technology an introduction to the packaging revolution. 

Journal of Electronic Packaging, Transactions of the ASME, American Society of Mechanical Engineers. Journal of Surface Mount Technology, published quarterly by the Surface Mount Technology Assn., 5200 Willson Rd., Suite 200, Edina, MN 55424-1338. 

The extent of these interconnect density issues is not always observable, but the chart in Rg. 2.1 can help one define and understand it. The chart portrays the interrelationship between component packaging, surface-mount technology (SMT) assembly, and PWB density. As can be seen, these three elements are interlinked. A change in one has a significant effect on the overall interconnection density. The metrics are as follows ... 

Figure 3.7 shows the variety of surface-mount plastic packages that have been developed based on PQFP technology. 

Materials with Enhanced Mechanical or Conduction Properties. In cases where the device package (leadless area array with ball grids) is incompatible with the CTE of a standard material, a low-expansion snbstrate mnst be nsed.This can be achieved in several ways. In the past, leadless surface-mount technology (SMT) focused on replacing the woven glass in standard FR-4 with woven quartz or aramid fibers. Although this reduced the expansion of the substrate, both materials were expensive and difficult to process. 

Connectors comprise approximately 75 to 80 percent of odd-form components. See Fig. 40.6. For example, there are universal serial bus (USB) connectors, dual inline memory module (DIMM) connectors, phone jacks, and zero-insertion-force (ZIF) connectors, as well as a variety of surface-mount connectors. Other odd-form components include sockets, electrolytic capacitors, transformers or large inductors, LEDs, relays, switches, as well as speakers and vibrators for handheld communications devices. In surface-mount technology, odd-form components are most often through-hole packages, including both passive and active devices as well as connectors. When addressing such odd-form components, the first step is to check the availability of an equivalent surface-mount version since there has been a shift toward surface-mount versions of many of these devices. Of course, the materials used to construct the surface-mount replacement must survive the reflow furnace environment, and especially the Pb-free reflow temperatures, particularly connectors because of their complex internal construction. In some cases, it has been possible to replace the through-hole connector with one of a variety of solderless products. 

Electronic packages are composed of complex materials that are assembled via intricate processes and then subjected to a wide range of service environments. It is crucial to note that both the die-packaging processes and surface-mount technologies can impart stresses and create residual stresses in the final packaged assembly that impacts its interconnect reliability. Assessing the rehabihty of package devices requires that all variables that can hinder or enhance reliabihty be considered. 

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