Subtype declaration

Once a subtype has been declared it can itself be used as the base type for further subtype declarations. Any two subtypes that are ultimately derived from the same unconstrained type can be mixed in one expression. However, it is important to ensure that the range constraints on both sides of an assignment statement are matched. For example, if two integer subtypes and two signals are defined as follows ... 

Common items that are found in packages include type and subtype declarations, functions and components. Types and subtypes that are implicitly accessible to any design are declared in the STANDARD package. This package cannot be modified by the user and is stored in die STD library along with another, TEXTIO. However, the type declarations and procedures that this contains cannot be used if a design is to be synthesized. 

If the t)rpe BIT had been declared as a subtype of XOIZ, and not a new type, the situation would have been different. The subtype declaration would have been as follows. 

Each model can have parameters, variables, equations, initial conditions, boundary conditions and submodels that can have submodels themselves. Models can be based in pre-existing ones, and extra-functionality (new parameters, variables, equations, etc.) can be added. So, composition hierarchical modelling) and inheritance are supported. Every parameter and variable in a model is based in a predefined type and have a set of properties like a line/description, lower and upper bounds, unit of measurement among others. As models, types can have subtypes and the object-oriented paradigm is implemented. Some examples of types declarations can be seen in Figure 2. 

Each object used in a VHDL description must be declared as a certain type or subtype. This will place restrictions on the value an object can contain and how the object can be manipulated. A type can be created that satisfies the requirements of a design, but a range of predefined t) es do exist. These are all stored in the STANDARD package within the STD library. Associated with each of these are a full set of standard operators (logic, relational, etc). 

A restriction placed on the range of values that a given type may take is called a constraint A subtype is any type with a constraint. Declaring an object as a type subjected to a constraint is equivalent to declaring a subtype. An unconstrained type does not have any restriction placed on the range of values that an object of that type may take. The four classes of types are ... 

The range values of an unconstrained array are defined when an object of that type are declared. The definition of this range is constrained by the type mark. For example, for the subtypes ... 

These declarations make use of the predefined attribute high. This is discussed in Chapter 7. The s)mtax for creating subtypes is given in Box 3.11. 

A subtype is a type with a constrained range of values. It is declared with the syntax ... 

If a constraint is not applied the subtype is exactly the same as the. type or subt) e from whid it is being declared. 

The form of the constraint expression is dependent upon the type or subtype from which the subtype is being declared. The following examples illustrate range constraints ... 

The range direction in the subtype must be the same as the subt)rpe or type from which the new subtype is being declared. 

Array types can be used in the declaration of signals, variables and constants. How to make assignments to objects of this type is discussed later in this chapter in Box 5.4. As a precursor to that, this section looks at the ways in which the elements of composite types can be manipulated for use as targets or sources in assignment statements. Consider the types, subtypes and signals declared below. 

A type definition on the other hand/ creates a new base type and may be constrained or unconstrained Consider the subtype defin in the package NEW PROC shown in Figure 5 2 This is a subt3 e of the imconstrained base type BIT VECTOR It may therefore use any function defined for that type or be used in assignment statements with other BIT VECTOR svhtypes. This was done in the SYNC WAIT architecture when the 4-bit BIT VECTOR REG was passed to the PRESET CLEAR procedure The following declaration also creates a 4-bit array of type BIT ... 

The function declarative part may contain declarations for subprograms, types, subtypes, constants, variables, attributes. It may also contain subprogram bodies, attribute specifications and use clauses. Several other declarations are not supported for synthesis. Every declaration made in this part is reset between calls. Initial values for objects will be ignored when synthesizing. 

The difference between resolved and unresolved types is discussed in Box 7.7. Of the two types declared in the STD LOGIC package, stdjogic is the one from which a variety of subt)q es are declared and sets the main standard. As already mentioned, the XOlZ is a subtype of this type, but others such as UXOlZ also exist. These can exploit the wide range of functions available for the type and at the same time maintain their portability. 

The multivalued logic systems outlined above are subsets and supersets of other systems. However, as the discussion in Chapter 3 on types and subtypes explained, objects of different types caimotbe university interchanged or equated. For example, given the type declarations ... 

A LEFT[(N)] (function) Any prefix A that is appropriate for an array object or an alias thereof or that denotes a constrained array subtype A locally static expression of type universaljnt er. the value of which must not exceed the dimensionality of A. If omitted, it defaults to 1. Left bound of the Nth index range of A. (If A is an alias for an array object then the result is the left bound of the Nth Index range from the declaration of A not that of the object). The result type Is the type of the left bound of the Nth index range of A... 

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