Solder level 3 interconnections

The capability to layer interconnection levels is critical for many complex circuit designs. One particular application called for assembling devices on a silicon wafer with solder connections. The necessary interconnection density was obtained by using two signal layers above the power plane separated by a dielectric Iayer.(j3... 

Term Reliability of Weifer-Level Packages with Sn-Pb and Sn-Ag-Cu Solder Interconnects, J. Electron. Mater. 40,2011,doi 10.1007/sll664-011-1705-y. 

Lead-free reflow may be done in air or N2. Typically N2 is not required, and the use of N2 may even increase certain defects (such as tomb-stoiflng) especially for small passive components. In certain situations, N2 may help improve wetting (which in turn may help reduce the amount of voids in the solder joints). For flip chip applications, where flux is used instead of solder paste, N2 becomes necessary to form reliable solder interconnects. An N2 atmosphere with O2 level below 1000 ppm has been found to be effective (Ref 65, 67). 

The widely recognized use of Pb-Sn solders in electronics assembly is in the Level 2 interconnections. Level 2 interconnections are solder joints that attach device packages to the printed circuit board. The solderability and, ultimately, the reliability of Level 2 interconnections are determined by the materials used for the package input/output (I/O) and those used for the circuit board. 

The Pb Sn solders, and primarily the eutectic 37Pb 3Sn and near-eutectic 40Pb-60Sn alloys, are used in the fabrication of Level 3 interconnections. Level 3 interconnections include cable-connector assemblies used to transmit signals between printed wiring assemblies as well as hard wired solder joints such as lead-to-turret or lead-to-eyelet intercormections. Examples of connectors are shown in Fig. 24. The Pb-Sn solder can be used in the actual construction of the connector, such as in the case of the coaxial cormector shown in Fig. 25, or in the attachment... 

FIG. 29 Examples of finite element meshes for Level 2 and Level 3 soldered interconnections (a) gullwing leaded package, (b) chip device, (c) pin-in-hole, and (d) connector. (Courtesy of Sandia National Laboratories.)... 

This CSP type uses a flexible circuit having solder balls or metal bumps as an interconnect interposer between the chip and the next circuit board level. The bare... 

Flex interposer-based CSPs. This CSP type uses a flexible circuit having solder balls or metal bumps as an interconnect interposer between the chip and the next circuit board level. The bare chip is attached facedown and wire-bonded to the interposer. A thin elastomer, sandwiched between the chip and interposer, cushions the chip and the solder-ball interconnects, relieving stresses (see Fig. 1.13). The interposer generally consists of a metallized, flexible polyimide tape on which are formed electrical connections by photolithographic processes. As a final step, the exposed wire bonds and edges of the chip are molded with epoxy. 

The FEM analysis has also shown that the stress of the first-level interconnection in the encapsulated flip chip bump is comparably same to that of the alumina package which has high hrst-level interconnection reliability. We evaluated the solder joint reliability of EGA and CSP by TCT. We confirmed that we could obtain approximately three to ten times longer fatigue life by this high TCE ceramic material package than that of an alumina material package 151. 

Use of bipolar electrodes to form an ES stack is shown in Figure 5.9. The bipolar arrangement can effectively minimize the volume of the stack and circumvent the use of additional materials and external connections. In addition, the intimate surface level connection can help overcome macroscopic resistances generated from solder joints, long interconnects, and tabs that contact only part of the collector foil. The reduction in packing material (grid weight) for a module also improves cell performance. 

---