Silicon thermal expansion coefficient

Casting Casting around steel parts, which are first hot dipped in aluminium or in aluminium-silicon alloy (the Al-Fin process), gives good bonding but requires careful design because of the different thermal-expansion coefficients of the two metals. 

Many different substrates are used fora-Si H deposition. Usually Corning 7059 glass [390] and crystalline silicon are used for materials research, as both have similar thermal expansion coefficients to fl-Si H. Devices are mostly made on... 

Pure crystalline silicon is a brittle material with a gray metallic appearance. Its mechanical properties, such as Knoop hardness (950-1150 kg mm-2), Young s modulus (190 GPa for (111), 170 GPa for (110), 130 GPa for (100)), torsion modulus (4050 kg mm-2) and compression breaking strength (5000 kg cm-2) vary slightly with crystal orientation. Silicon has a low thermal expansion coefficient (2.33x 1(T6 K-1) and a high thermal conductivity (148 W K-1m-1). Crystalline silicon melts at 1413 °C (1686 K). 

The thermal expansion coefficient of bulk silicon is positive at RT (2.6 x 1CT6 K-1), but becomes negative below 120 K. The thermal expansion coefficient of micro PS for heating from 290 to 870 K is found to be negative (-4.3x 10 6 KT1), which can be ascribed to hydrogen desorption and oxidation of the inner surface [Di7]. For meso PS the thermal expansion coefficient was found to increase with porosity in the temperature regime between 90 K and 300 K, from 0.4xl0-6 K 1 to... 

The thermal expansion coefficient of silicon is approximately seven times larger than that of Si02, as given in Table 2. When Si02 is deposited, typically at temperatures of several hundred degrees C, an in-plane compressive stress develops in the oxide layer as the Si wafer is cooled by AT to room temperature. For a uniform 2-dimensional thin film deposited on a substrate, the in-plane stress obtained from Equation 2 is ... 

Figure 12.4 Bending response of a cantilever (as measured by the voltage output from a position-sensitive detector) to applied voltage pulse with and without TNT adsorbed on the surfaces. The bending of the uncoated cantilever follows the time profile of the applied voltage pulse (except the lengthening of the rise and fall times) and is presumably due to the difference between the thermal expansion coefficients of silicon and the doping material. The exothermic nature of the TNT deflagration event is clear due to the enhancement in bending of the cantilever.

The thermal conductivity of diamond at 300 K is higher than that of any other material, and its thermal expansion coefficient at 300 K is 0.8 x 10". lower than that of Invar (an Fe-Ni alloy). Diamond is a very widc-band gap semiconductor Eg = 5.5 eV), has a high breakdown voltage (I07V cm-1), and its saturation velocity of 2.7 x I01 cm s-1 is considerably greater than that of silicon, gallium arsenide, or indium phosphide. 

The low water absorptivity and good resistance to hydrostatic pressure make syntactic foams very useful for marine and submarine construction. Materials to be used for deep-sea application must have 1) low compressibilities at high hydrostatic pressure, 2) low thermal expansion coefficients, 3) low water absorption, and 4) good fire resistance. The fluids used for buoyancy in deep water submersibles include gasoline, ammonia, and silicone oil, while the solids include plastic, glass and aluminium foams, lithium, wood, and monolithic polyolefins. The liquids are dense but have low... 

When a composite is subjected to external forces, the energy of the matrix is only transferred to the fibres when there is question of a proper attachment. For that reason fibres are some-times provided with a layer of another material. An example boron fibres in an aluminium matrix are provided with a silicon carbide coating and as a result the fibres are called borsic fibres. The thermal expansion coefficient of a fibre and its matrix must correspond. Figure 14.9 is a representation of what takes place when a crack in a fibre-reinforced matrix grows. 

The problem of cross-talk between adjacent photodiodes and the problem of different thermal expansion coefficients between a silicon substrate and an HgCdTe substrate are approached in JP-A-63281460. A detector is made up of HgCdTe wells, comprising photodiodes, formed in a CdTe substrate. The detector is bonded to a silicon substrate by a flip-chip process, and finally the CdTe substrate is etched away. 

The problem of difference in thermal expansion coefficients between an HgCdTe substrate and a silicon read-out substrate is addressed in JP-A-2214159 where a design similar to the design of JP-A-63296272 is presented. 

To reduce the effect of difference in thermal expansion coefficients between a silicon readout substrate and an HgCdTe detector layer, which is bump bonded to the silicon substrate, it is proposed in JP-A-1061056 to affix a second silicon substrate to the HgCdTe detector layer with an intermediate layer of GaAs. 

The invention of US-A-536S088 approaches the problem of stresses generated by the mismatch of the thermal expansion coefficients of HgCdTe and silicon by including a buffer layer of sapphire. The characteristic thermal expansivity of sapphire is more similar to the thermal expansivity of HgCdTe than that of silicon. 

Mechanical stress in connection bumps formed between a read-out circuit in a silicon substrate and detectors in an HgCdTe substrate due to a difference in thermal expansion coefficients of the two substrates is reduced in US-A-4943491 by bonding a layer of a material, having a greater thermal expansion coefficient than the coefficient of the two substrates, to the silicon substrate. 

When the flip-chip technique is used to connect two chips of different materials having different thermal expansion coefficients, the connection will be subjected to mechanical stress to a degree dependent on the the thermal history of the array. In JP-A-55150279 (Fujitsu Ltd, Japan, 22.11.80) the connection between an HgCdTe detector chip and a silicon read-out chip comprises bent buffers which absorb such mechanical stress and which prevent the fragile detector chip being damaged during the connection. 

The hybrid circuit 10 comprises a buffer structure 16 which is comprised of a material which accommodates the difference in thermal expansion coefficients of the HgCdTe detector array 12 and the silicon read-out chip 14. The buffer layer is made of sapphire which also has good thermal conductivity properties. The buffer structure has laser drilled vias 18 which are formed in registration with unit cells of the detector array and the read-out circuit. Each of the vias is provided with indium bumps 20 at opposing ends thereof. The buffer structure is interposed between the detector array and the read-out chip. Cold weld indium bump technology is employed to couple the bumps 20 to the buffer structure. The buffer structure is further... 

A focal plane array is formed in a substrate 10 of HgCdTe. The substrate is bonded by indium bumps 20 to a multiplexer circuit formed in a silicon substrate 30. A copper layer 30 is bonded to the silicon substrate by means of an adhesive layer 40. The copper layer has a thermal expansion coefficient which is greater than the coefficient of HgCdTe and silicon. 

The difference of thermal expansion coefficient between an HgCdTe detector material and a silicon read-out material is dealt with in FR-A-2494910 where detector elements in the shape of islands are connected on one side to a silicon read-out chip and on the other side to a substrate having a similar thermal expansion coefficient as the silicon read-out chip. 

Individual detector elements 4 of HgCdTe are formed into islands which are connected on a first side via indium connectors 3 to input regions 11 of a read-out chip 1. A second chip 2, which is transparent to infrared radiation L and which comprises common electrodes 22, is connected to an opposite side of the detector elements via indium connectors 21. It is important that the thermal expansion coefficient of the chip 1 and 2 are closely matched. Both chips may, for example, be made of silicon. 

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