RC delay

Reduction in resistive and capacitive (RC) delays is continuing by the use of higher conductivity materials and improved ohmic contact. 

As the size of microchips evolves from 130nm to 90nm or smaller, the increasing packing density between multilevel interconnects will lead to severe RC delay, power consumption and wire cross talk, which are the major factors limiting device performance. As a consequence, the design of novel semiconductor materials with desired chemical and physical properties has stimulated intense experimental and theoretical efforts. For example, there have been ongoing activities to develop materials with low dielectric constants (k) to replace the current silicon dioxide (k = 4.0) wire insulator. A particularly active area of research in the past few... 

The dielectric layers should be thick to achieve low interconnect capacitance (or high characteristic impedance), which reduces the power consumption of driver circuits and the RC delay of the Interconnect. Finally, the dielectric material should have a low dielectric constant (e ) to minimize the propagation delay (which is limited by the speed of light in the dielectric), the interconnect capacitance and the crosstalk between signal lines. 

FORMATION OF FUNCTIONAL MICROSTRUCTURES 1.3.1 RC Delay and New Interconnect Materials... 

The two key components in interconnect delays include the inherent resistance (R) of the metal lines and the capacitance (C) of the dielectric material in between the lines. The so-called RC delay is defined as the time required for the voltage at one end of a metal line to reach 63 % of its final value when a step input is presented at the other end of the line [18] ... 

The first generation of the interconnect material is aluminum with a resistivity of p = 2.66 pQ cm. One approach to reduce RC delay is to switch to an interconnect material with lower resistivity as indicated by Eq. (1.1). A wide range of metals was considered as a potential candidate in the early 1990s. Gold has excellent resistance to corrosion and electromigration but its conductivity is similar to that of aluminum. Silver has the lowest resistivity (p = 1.59 pQ cm) but poor resistance to corrosion and electromigration. Hence, copper that has a resistivity of 1.67 pO cm and excellent resistance to electromigration was selected. Compared to aluminum, copper has one drawback. It cannot be deposited by RIE. Therefore, a copper interconnect is typically formed via a damascene process in which a pattern is first etched into the dielectric and overfilled with copper. The excess copper above the... 

Equation 2.3 suggests that the RC delay is not dependent upon line width and therefore should not change as line dimensions are decreased. However, often when feature sizes are scaled on an IC, the line thickness and the ILD thickness are scaled down but, as a result of increasing chip complexity, the line length remains constant. As a result, the RC delay does increase as dimensions are scaled. 

From Equation (2.3), the RC delay is directly proportional to the dielectric constant of the ILD. By switching from oxide-based ILD to a low e, ILD material, significant gains may be obtained in decreasing the interconnect delay. In addition, lowering dielectric constant lowers cross talk due to capacitive coupling between adjacent metal lines and power dissipation which is given... 

J. Christiansen, M. Mota, A high-resolution time interpolator based on a delay locked loop and an RC delay line, IEEE Journal on solid state eireuits 34, 1360-1366 (1999)... 

New materials are applied to maximize the capacity of device. To increase the capacitance of cap used in DRAM, sfudies about high-k dielectric material are in process. Elash memory uses a gate material with polysilicon by reason of high speed and stable storage. To reduce semiconductor device RC delay, Cu metal lines and low-k are being introduced. This section represents the concept of CMP processing being introduced to DRAM and NAND flash devices. 

Alpert CJ, Devgan A, Kashyap CV (2001) RC delay metrics for performance optimization. 

The series RC circuit can play a role in describing this phenomenon, since it is a passive low-pass filter. More precisely, an RC transmission line or infinite RC delay line may be used to model the battery voltage relaxation after operation. Expressing the voltage change with respect to time through this line leads to a partial differential equation equivalent to Pick s second law (Equation 9.59). 

Another method to estimate the real surface area in materials like TiN which inject charge capacitively is cyclic voltammetry. Due to the intrinsic delays present in the topography of electrode surface structures (pores RC delays) explained above, the large interface capacitance of TiN measured with slow cyclic voltammetry is not available at fast rates of current injection [4]. 

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