Rambus DRAM

A bank is actually a DRAM array composed of 1024 rows of 256 dualocts . A dualoct contains 16 bytes and is the smallest unit of memory that can be addressed in a RDRAM. Since neighboring banks could share a group of sense amplifiers, only 16 out of the 32 banks can be active at the same time. 

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Keywords 2.5-D integration, crossbar, Rambus DRAM, reconfigurable data-path, microprocessor, memory, latency. 

Figure 3.3 illustrates the internal organization of atypical 128 MB Rambus DRAM chip. The memory is organized into 32 banks with each bank holding 4 MB data. 

If the 2.5-D technology is available, it s possible to re-organize the RDRAM chip so that the signal path can be significantly reduced. Suppose we need to design a memory system composed of four RDRAM chips. In the conventional solution, the four chips will be serially connected as shown in Fig. 3.5. In a 2.5-D stacked memory system illustrated in Fig. 3.6, the DRAM cells can now be placed into four layers and vertically stacked. The memory bus will be through inter-chip contacts, which have only a vertical height of <50 pm. As a result, 2.5-D stacked Rambus DRAM has a considerable potential to achieve superior performance at a relatively low cost. 

The DRAM is also assumed to be built in a 0.13 pm process. The memory bus between L2 cache and DRAM is placed in the middle of the L2 cache, which is marked as red rectangles in Fig. 3.10. The DRAM will be placed on the top of the microprocessor in a way illustrated by Fig. 3.11. As for the main memory, we selected a high-end, Rambus DRAM with a clock of 1 GHz. Since the CPU clock has a frequency of 4 GHz, the access cycle time of the main memory is 4 CPU cycles. In the remaining part of this section, the word cycle always refers to a CPU cycle. On the other hand, the memory latency value is usually determined by the specific machine configuration and typically values are in the range of 100 cycles to 500 cycles (e.g., [20]). Because our target microprocessor is very aggressively clocked, we assume a memory latency of 400 cycles. 

J. Stokes. Ars Technica RAM Guide, Part III DDR DRAM and RAMBUS, [online]. Available http //www.arstechnica.eom/paedia/r/ram guide/ram guide.part3-l.html. 

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