3-D memory stack

Figure 5.18 3-D memory stack. Source Vertical Circuits, Inc.

A nanostore is a single-chip computer that includes 3-D stacked layers of dense silicon non-volatile memory with a layer of compute cores and a network interface. A large number of individiral nanostores can cottununicate over a simple interconnect and run a data-parallel execution environment like MapReduce to support large-scale distributed data-centric workloads. The two most impor-... 

If the 2.5-D technology is available, it s possible to re-organize the RDRAM chip so that the signal path can be significantly reduced. Suppose we need to design a memory system composed of four RDRAM chips. In the conventional solution, the four chips will be serially connected as shown in Fig. 3.5. In a 2.5-D stacked memory system illustrated in Fig. 3.6, the DRAM cells can now be placed into four layers and vertically stacked. The memory bus will be through inter-chip contacts, which have only a vertical height of <50 pm. As a result, 2.5-D stacked Rambus DRAM has a considerable potential to achieve superior performance at a relatively low cost. 

General purpose registers and memory (Fig. 3 (c) and (d)). The outcome distributions for general purpose registers and memory follow a similar trend. These locations typically store either data or addresses. If they hold an address, the impact of an error is likely to be similar to the impact of errors in the stack pointer, where errors in bit 17 to 22 always raise a hardware exception. (Note that the results for the stack pointer register (Rl) are not included in this data.)... 

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