PODER technique

Table 4.5 Area and performanee of miniMIPS and the hardware module used by PODER technique synthesized in 0.18 p CMOS process technology 45...

Table 6.1 Classification of the total 48,323 faults in the miniMIPS protected by PODER technique with VAR and BRA 71...

The PODER technique is the first novel hybrid technique presented in this book. It was initially based in the CCA technique and its two-element queue to keep track of the changes in the program s control flow, called BID and CFID. The technique aims at detecting a few types of control flow errors, such as (1) incorrect jumps to the beginning of a BB, (2) incorrect jumps inside the same BB, (3) incorrect jumps to unused memory addresses, and (4) control flow loops. It is important to mention that PODER cannot detect errors in branch instructions, where a path should have been taken, but was not taken, and vice versa. In order to do so, it must be combined with the Inverted Branches software-based technique, described previously in Sect. 4.3. 

Original unhaidened PODER technique Combined techniques... 

Table 5.1 Percentage of number of error from fault injection results for PODER fault tolerant technique in miniMIPS running the matrix mirltiphcation 66...

In the following sections, we will present the HPCT tool to automatically transform program codes into hardened ones, two known software-based techniques, called Variables and Inverted Branches, and three novel hybrid techniques to detect transient faults in embedded processors, named PODER, OCFCM, and HETA, combined with the previous known software-based techniques. 

The technique is divided in software-based and hardware-based sides, which communicate through memory writes at predefined memory addresses. In order to do so, PODER exploits two main concepts ... 

In order to detect such errors, PODER uses the communication between software-based techniques and hardware-based techniques. It does so by calculating a second signature for each BB, called XOR, during compilation time (by the software-based techniques), and during runtime (by the hardware module). The XOR value equals to the result of the operation exclusive OR (XOR) between all the instmctions from the BB. 

Tables 4.3 and 4.4 show the original and modified program s execution time, code size, and data size for the matrix multiplication and bubble sort algorithms, respectively. They present results for the original unhardened program, as well as the version hardened with PODER and hardened with PODER combined with the Inverted Branches and Variables software-based techniques (Combined Techniques).

This technique improves PODER because it can detect all errors detected by PODER (incorrect jumps to the beginning of a BB, incorrect jumps inside the same BB, incorrect jumps to unused memory addresses and control-flow loops) only by using a non-intrasive hardware module. The main drawback is that it is apphcation-specific and therefore is not as simple to be applied to a General Purpose Processor (GPP) as PODER. 

OCFCM itself is defined as a non-intrasive hardware module and therefore corrld be considered a pure hardware-based technique. Irrstead, OCFCM alone cannot achieve its main objective, which is detecting control flow errors. To do so, it has to be complemented by the Inverted Branches software-based technique (described in Sect. 4.3) and configured by the apphcation running in the processor. Because of these characteristics, it is considered as a hybrid farrlt tolerant technique, even if not as tightly coupled with the software-side as PODER. 

The technique has a clearer division between software arrd hardware than PODER, since the communication between them is very restricted. The division follows two main concepts ... 

Hybrid Error-detection Technique using Assertions (HETA) is the third and final hybrid technique presented in this book. It was initially based in the CEDA software-based technique and its abiUty to efiSciently detect control flow errors between different BBs, and PODER and its ability to detect control flow errors inside the same BB. HETA is aimed at both FPGAs and ASICs, since it implements a non-intrasive hardware module combined with transformation rules on the program code. 

It is important to note that HETA, like PODER and OCFCM, cannot detect incorrect but legal jumps (according to the program graph). In order to do that, the Inverted Branches software-based technique, described in Sect. 4.3 is required. Also, HETA may present aliasing, when the program code has many BBs. With big apphcations, some signatures may start to repeat themselves and an error may not be detected by the technique. 

Like PODER and OCFCM, HETA can also detect control flow loops (4). In order to detect this kind of error, a watchdog timer is implemented. The counter is reset every time the software-based technique side enters a BB, by performing a Reset XOR instruction. When the counter overflows, an error is flagged. By doing so, the hardware module can detect a control flow loop that causes the execution flow to be stuck at a single instruction. 

Such results show that VAR and BRA combined with PODER can be used in harsh environments and allow designers to reach fast fault diagnosis and correction. When comparing to hardware-based techniques, such as TMR, we can notice an area reduction higher than 66 % and still acceptable fault coverage of 98.3 %. On the other hand, the hardened application takes 2.34 times the original execution time and requires 15 % extra area for the hardware module. 

In terms of diagnosis. Table 6.2 shows the number of faults and errors in the DUT that were detected by the implemented techniques. PODER was the technique... 

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