Paralleling Output Capacitors

On a typical one-sided board (still very common in commercial AC-DC power supplies), as the number of capacitors you try to parallel goes up, so does the intervening PCB trace impedance. Take, for example, Figure 5-1, where we have the simple case of one output capacitor. A small advisory here—if you try to reduce the impedance further by making the current loop smaller and smaller, the capacitor would eventually start comparing notes with the heatsink on the topic of temperature, and that can t be good for its life expectancy. 

In the Boost and the Buck-Boost, we see that the output capacitor is in the critical path. So this capacitor should be close to the control IC, along with the diode. A paralleled ceramic capacitor can also help, provided it does not cause loop instability issues (especially in voltage mode control). 

In high-power offline Flybacks, the trace inductances on the secondary side reflect on to the primary side, and can greatly increase the effective primary-side leakage inductance and degrade the efficiency. The situation gets worse when we have to stack several output capacitors in parallel, just to handle the higher RMS currents. Long traces seem inevitable here. This has been discussed in detail previously. 

In the buck however, note that though the output diode needs to be positioned close to the IC/switch, the output capacitor is not critical (its current is smoothened by the inductor). If we place a ceramic capacitor in parallel to the output capacitor, it is only for the purpose of decreasing high-frequency noise and ripple at the output even further. But it is really not mandatory, and can cause severe loop instability, particularly with voltage mode control, especially if the effective series resistance (ESR) of the output capacitor section becomes too low (less than 100 inQ typically). 

Diagram 2 illustrates the principle of the analog memory for a 2-channel 8-word system. Each capacitor is connected to the signal line via its individual switch which is open (0) or closed (1) according to the logic output of the corresponding bit of a parallel output shift register. 

The output of the detector is proportional to the capacitance difference. Let A be the overlapping area between plates and d the distance (gap) between them. If d is much smaller than the plate dimensions, the capacitance of a parallel plane capacitor is... 

Example 8.2. A parallel plate capacitor transducer is used to measure displacement. One plate of the capacitor is fixed, and the other is free to move with the input displacement. The capacitor plates each have an area A, and are separated by a distance d. The dielectric constant of the medium separating the plates is e. The output of the capacitor transducer is applied to a modified capacitance bridge which measures the fractional capacitance change, ACjC, rather than the absolute variation AC. What is the nature of the response characteristic ACjC versus Ad/dl... 

To properly design the capacitance for the output stage, one should place enough capacitors in parallel so that each capacitor operates at about 70 to 80 percent of its maximum ripple current rating. The sum of the capacitors should equal the final calculated value, but each capacitor should have the value of Ctot/fi, where n is the number of capacitors in parallel. 

As one can see, there is the familiar choke input filter (T-C) on the output, which is characteristic of the buck and all forward-mode converters. The configuration shown in Figure 4—10 is called a parallel resonant topology because the load impedance (the T-C filter acting as a damping impedance) is placed in parallel to the resonant capacitor. The input to the T-C filter stage... 

The best candidate capacitors are from AVX. They have very low ESR and thus can handle very high levels of ripple current. These capacitors are exceptional. I will place two pieces of the following parts in parallel on the output. 

These cause dynamic issues to the switching power supply, and usually the only solution to that is to have enough bulk capacitance present on the 12V output rail. Luckily, since the main feedback loop is derived from the primary 5V/3.3V rails of the power supply, there is no minimum ESR requirement for the 12V rail output capacitance, and we can freely add several electrolytic capacitors in parallel. However, modern core processors can place very fast transient load demands on the primary regulated rail, too, and for that we need a whole bunch of ceramic capacitors sitting right at the point of load. In that case we must ensure the converter is designed to accept ceramic loads. Otherwise it will break up into oscillations. 

Incidentally, don t blindly add a bypass capacitor in parallel with the (upper) feedback resistor, as suggested. That feedforward capacitor introduces another zero in the loop and can cause the system to go unstable. You should realize that this family of devices has a full-blown internal Type 3 compensation, so it even has an internal zero to emulate an external ESR zero. That is why this family is supposed to be able to handle ceramic capacitors at the output. If you introduce yet another zero (via the feedforward capacitor as suggested), you could have one too many zeros. And ultimately, your design could be one, too (a zero). 

---