How to Parallel Output Capacitors for Proper Sharing

Typical 5 V output p ower supply component parameters Universal input (85-265 VAC) 

We all know that the losses in the output capacitor of any Flyback are high, due to the choppy waveform of the current they encounter coming through the diode. It is obvious that reducing the ESR to zero would totally knock off a major chunk of losses, boost the published efficiency curves, and allow a much higher maximum achievable power for the device. However, OmQ would have been much too obvious, wouldn t it So it was a case of Buck the ESR and Boost the efficiency. In other words, a perfect Buck-Boost. 

My problem was that the company now expected me to somehow validate the efficiency curves. They were perhaps overly sensitive about possible legal complications, such as, if the customer demands to see a working board to reaffirm the datasheet, and there happens to be none. Quite like stock options with no dates to back them up. 

So after having created the math spreadsheets and having improved the efficiency curves, I actually had to do the impossible now. I had to build it. What worried me was not just the fact that I had to obviously parallel over 10 large capacitors to get an effective ESR close to the target, but the fact that I had to ensure that the impedance of the intervening PCB traces also virtually canceled out. 

There is also a major issue concerning secondary-side trace inductances, one that we will discuss a little later. Other than that, there are no issues, except of course the fact that because there is only one capacitor, the effective ESR won t be very good (nor the RMS ripple current-handing capability). 

---