Objectives and Book Organization

As indicated in the previous sub-sections, IC industry will have to take major efforts to develop the 3-D stacking technologies. In this book we will focus on a small but important set of elements of these efforts that may be useful to initiate activities in design technology for 2.5-D integration. Specifically, the objective of this research is to provide a thorough feasibility study on the 2.5-D integration 

Cost Analysis First, we are going to establish a unified cost analysis framework to compare the fabrication cost of different integration schemes. In fact, given a VLSI application, there are many different ways to build it on silicon. Accordingly, the first research objective is to provide an apple-to-apple cost comparison for different integration styles. 

5- D ASIC Physical Design Automation For ASIC designs, it s not feasible to find an optimized 2.5-D implementation manually. Therefore, we have to build the first-generation 2.5-D layout design tools to automatically implement stacked layout. Then we can compare the interconnect characteristics between the monolithic and 2.5-D layout implementations of a give system and thus assess the feasibility of the 2.5-D paradigm. 

In the remaining parts of this book, we would cover our journey toward a feasibility evaluation on the 2.5-D integration paradigm. The succeeding chapters are organized as follows  

In Chapter 2, we present a unified cost analysis among five different integration schemes monolithic System-on-Chip, Multiple-Reticle-Wafer, Multi-Chip Module, 2.5-D integration, and 3-D integration. Our results proved that the 2.5-D integration scheme could be the most cost efficient under a group of reasonable assumptions. 

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