Storage element inference

Inferring storage elements is a mor complex process than instantiating them for three reasons. 

The clocked processes infer storage elements. The counters designed in Chapter 5 investigated the types of D-type flip flops that are implemented under different circumstances. It should be easy to predict which will be used in these registers. 

When and where to use clock statements. Espedally important here is the understanding of the likely structure needed before designing die circuit logic. This will determine whether it is better to instantiate or infer storage elements (sections 5.1.2 and 5.1.3). 

In Verilog HDL, a register variable retains its value through the entire simulation run, thus inferring memory. However, this is too general for synthesis. Here is an example of a variable that is used as a temporary and therefore need not be a candidate for a storage element. 

A flip flop or any storage element is inferred inside a Process statement. The template that indicates a sec]uential logic section is formed from either a Wait statement or an If statement. 

How does the designer know what the synthesizer will produce This chapter should make dear the structure of inferred sequential logic circuits. However, the actual choice of storage element made by the synthesizer is one aspect of the design that is most often very difficult to predetermine. Although a library may have a range of different types av able, indud-ing JK and SR types, the standard choice is usually a variant of tihe D-t5q e. Any additional logic to implement a different type is then constructed on the front end of this. 

The same rules can be applied to arrays of signals and variables. In such a case, if one element of the array infers a storage element then so do all die elements. Level-sensitive latches are a special case discussed in section 5.4.4. 

The most common and definitely the best way of achieving this is to attach an external asynchronous or synchronous reset signal to each and every storage element in the circuit. When an external initialization signal is specified, the compiler will select an appropriate component from the library (if the elements are inferred). For example, if a flip flop is required to be initialized to V, the selected element will possess an input for a preset signal. A variety of designs based on this form of initialization are given in the examples in this chapter. 

Below the top level (inside the process), most of the synthesized circuits are different. The process in SIMPLE constructs the circuit shown in Figure 5.14. This is the most basic demonstration of how a signal assignment inside a process with a clock expression template will infer flip flops. The synthesizer has used the most basic storage elements available - edge-triggered D-t)rpes. 

If the signal (or variable) infers a storage element (in a synchronous section elsewhere) then the logic of the assignment becomes part of the asynchronous combinational input logic to the storage element. 

If the signal (or variable) does not infer a storage element the undefined state is considered to be a don t care. 

The If and Wait statement templates demonstrated in this chapter are all used to infer edge-triggered storage elements. It is also possible to infer level-triggered elements - transparent latches. This can only be achieved with an If statement, again inside a process. However, the synthesizer does not use a clock expression template. The sequential block should take the form of the example shown below. 

The important characteristic of this If statement is that REG (which could also be a variable) should be previously unassigned. When it is read in the assignment statement a value must be provided from somewhere and so storage elements are inferred. For the whole time that CLK is higK if X changes the value of REG must also be modihed. Hence, the storage elements must be transparent latches. 

Level-triggered storage elements (transparent latches) can be inferred using a level detection condition in an If statement, which then reads a previously unassigned signal or variable. 

Thus, the Decoder has been implemented as a component. Figure 7.4 shows the VHDL description of this circuit, which demonstrates how to construct a state machine. It is always advisable to use enumerate type encoding for states as shown in the architecture s declarative part. This example has eight states, inferring three storage elements and using all possible permutations of 0 and I. The present state is stored on a signal PRESENTSTATE that is visible only to this architecture. 

Restrictions on the content of clock statements. It is far too easy to create storage elements that require components which may it may not be possible to synthesize (e.g. a device with bodi a synchronous dear and asynchronous preset) using a particular library. (Qiapter 5 showed how a number of different D-types could be inferred.)... 

The full set of equations was used to model experiments from the literature using numerical methods. In one of these experiments [3], a clay sample in a flexible wall permeameter was subjected to a salt concentration gradient and salinity and pressure profiles were measured. In [4], a scripted finite element solver was used to provide numerical simulations. Using a least mean squares fit, the storage parameter and the reflection coefficient were inferred from the experimental data. Relevant parameters for this experiment are shown in Table 2. 

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