HAL System

The HAL (Hardware Allocator ) system was Paulin s thesis work at Carleton University. HAL includes scheduling, data path synthesis, and design iteration. 

The FDS and FDLS algorithms can also be used together to explore the design space. The FDS algorithm is used first with a maximum time constraint to find a near-optimal allocation then the FDLS algorithm is used with that allocation to tiy to find a faster schedule. 

Done by the InHAL module, using a force-directed scheduling algorifiim that tries to schedule the operations so as to balance the distribution of operations using the same hardware resources, without lengthening the schedide. First, both an ASAP schedule 

Constraints can be placed on the total hardware cost, or on the number of functional units of each t3q e. 

Done by the InHAL module, first scheduling the operations on the critical path, then the others. For the others, both an ASAP schedule and an ALAP schedule are generated, and the results combined to indicate the possible control steps for each operation. Operations are distributed when possible to minimize the scheduling of similar operations into the same time step. The MidHAL module is Ihen called to estimate the allocation of operations to functional units, and operations are reassigned when necessary to minimize the scheduling of operations using similar resources into the same time step. Note that there is no mention here of force-directed scheduling. 

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The data stractures used in the HAL system to represent control blocks support the movement of dataflow operations across control boundaries in a very natural fashion. These data structures allow us to make use of the force-directed scheduling framework directly, even in the ivesence of complex conditionals. 

Contrary to many control data-flow graph formats, the if-then else and case control blocks of the HAL system do not have any implicit boundaries [4]. The control blocks only serve to indicate which operations are part of which branch. Fork and join blocks can be nested to any depth. An example with multiple nested foik/join blocks is presented elsewhere [3]. 

In the HAL system, the time frames of the data flow operations are only dependent on other data flow operations. In Figure 8 for example, the +4 operation could be scheduled before the fork operation. As illustrated in Figure 10, the time frames of data flow operations extend beyond the time frame of the confrol block. Operations that are declared outside of the control block (e.g. +1 and +2) can be scheduled within the time frame of the control block. Whenever this occurs, the result is that the operation will be executed over all branches of the conditional block. 

Once scheduling and functional unit allocation are completed, the data path allocation can be performed. Two of the most important subtasks are register and interconnect allocation. In the HAL system, they follow the three transformation steps [2, 4] summarized below. The emphasis throughout the process is on the minimization of interconnect costs as represented by multiplexer and bus areas. This emphasis is justified by McFarland s experiences [14] which show that multiplexing costs seem to have the most significant effect on the overall cost-speed tradeoff curve. 

The DiffEq example depicted earlier, was first presented in an early DAC paper [2] and used subsequently in the Splicer [16] and Catree [17] systems. The summary of costs for Aese and the HAL system is given in Table 1. interconnect, register and functional unit costs are given relative to the results of an early version [2] of the HAL system (which is normalized to a value of 100%). 

In the Hrst four columns, non-pipelined functional units are assumed. The early HAL result was improved on by the Splicer and Catree systems as indicated in the second and third columns. The foi column refxesents the result obtained in the current HAL system using the register and bus merging algorithms described above. The table shows that the HAL register cost is equal to the best result achieved in the other systems, while the interconnect costs are significantly lower. 

Another facet of the second generation HAL system is a new methodology [31] for high-level controller specification and synthesis which is partly based on the concepts of Harel s statecharts [32]. The long term goal is to create a high-level synthesis environment which supports both DSP style q>plications as well high-level controllor applications (such as protocols). 

In the important 6-membered rings, (10) forms either a transition structure or an ion pair (gas phase). The reaction involves a transition structure for (H-Hal) systems (Hal=F,Cl) with A H formed by (H Hal). For instance, the reaction with (HF) (multiple cyclic proton exchange, model for proton exchange on pF])... 

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