Design space exploration

If it was practical to use as many hardware resources as operations to synthesize a given behavior, then each operation could be implemented by a dedicated hardware resource. In this case, hardware sharing dependencies would not exist and the (fetation execution order would only be constrained by data dq en-dencies and synchronizations. However, the assumption of dedicated hardware resources is often not appropriate for large-scale designs for two reasons. First, the size of the dedicated implementation would typically make it impractical. Second, the interconnection delays would probably not be negligible, and thwe-fore the resulting hardware would not be the fastest achievable implementation in practice. 

Synthesis across the hierarchy. As described in Chapter 4, the sequencing graph model supports two forms of hierarchy calling hierarchy, which refos to the nesting structure of model call vertices, and control-flow hierarchy, which refers to the nesting structure of conditionals and loops. 

Recall from Section 4.3 that a call vertex in a sequencing graph corresponds 

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Automatic module binding and transformation to meet constraints, design space exploration, and a PDP-8 example. 

The Value Trace, transformations on the Value Trace, and design space exploration using the transformations (on paper) to produce various PDP-11 architectures. 

Scheduling, data path synthesis, design space exploration, the AM2910, the AM2901, and the IBM System/370. Essentially Tseng83 + Tseng84a. 

Design space exploration and results for the AM2910 and the AM2901. 

M. Balakrishnan and P. Marwedel, Integrated Scheduling and Binding A Synthesis Approach for Design Space Exploration , Proc. of the 26th DAC, pages 68-74, June 1989. 

This machine has shown how input costs can be varied in EMUCS to allow for a design space exploration and to allow particular technologies to be targeted in the data path allocation phase. 

The PBS can be created by using different means, like a component modeling tool (e.g. Papyrus for EAST-ADL ). The downside of this approach is that the usage of a dedicated modeling tool may introduce additional constraints or the need to specify not yet available information. This requires design decisions which reduce the freedom for design space exploration in later stages of the development process. 

The complete SSIM resides in memory during high-level synthesis, thus achieving the necessary speeds for design space exploration and interactive design. 

The polynomial-time complexity of the above steps allows relative scheduling to be effectively integrated within the design space exploration. 

Beltrame, G., Bolchini, G., Fossati, L., Miele, A., Sciuto, D. ReSP A non-intrusive Transaction-Level Reflective MPSoC Simulation Platform for Design Space Exploration. In Asia and South Pacific Design Automation Conference, ASPDAC 2008, pp. 673-678 (2008)... 

Polstra, S., Pronk, T. E., Pimentel, A. D., Breit, T. M. (2008). Towards design space exploration for biological systems. CIRP Journal of Computers, 3(2), 1-9. 

Component based engineering applied to design space exploration comprising multi view/multi criteria architecture trade-offs, together with development and implementation. 

The sequencing graph model is the underlying representation for design space exploration, which is described in the next chapter. Relative scheduling, constrained conflict resolution, and relative control synthesis and optimization are all formulated based on the constraint graph model. 

Before describing the design space exploration strategy, we introduce first the concept of concurrency factor to measure of the degree of parallelism among subsets of shareable operations Q Q V. This concept is used extensively in resource allocation and heuristic exploration of the design space. 

Pruning ensures that pruned allocations or bindings always violate the required timing constraints. However, many bindings may still result even after pruning. This leads to the heuristic design space exploration strategy, described in the next section. 

Figure 5.11 Block diagram of subspace generation strategy for heuristic design space exploration.

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