Sequencing graph

Muirhead s ordering conditions in the above case are a chain on five vertices because all successive sequences (= graphs) are comparable. 

Uses a sequencing graph model, called the Sequencing Intermediate orm (SIF), for scheduling and allocation. The vertices of the graph represent operations to be performed, and the edges represent predecessor / successor relationships (which are subject to the data dependencies between operations). 

The input to the structural synthesis phase consists of a sequencing graph model of the hardware behavior to synthesize, along with the following constraints, which can either be specified in the input hardware description, or entered in-tCTactively by the designs. 

Formulating the Design Space. More specifically, a resource pool is a set of hardware resources (e.g. implementations of models) with an upper-bound on the number of instances of each type of hardware resources that the user allows in the final implementation. A resource binding is a matching of the operations (i.e. the vertices of the sequencing graph) to specific resources in the... 

Example Sequencing graph model Implementation Resources ... 

Sequencing Intermediate Form (SIF) A hierarchical sequencing graph is used to capture both control-flow and data-flow at the structural synthesis level. 

Behavioral transformations operate on the BIF model, which is generated by parsing the input HardwareC description. Upon completing the behavioral transformations, the optimized BIF is translated to the sequencing graph representation described in SIF. 

The input to Hebe consists of a sequencing graph model and the following constraints ... 

Conflict resolution, relative scheduling, relative control synthesis and optimization are formulated on a constraint graph model that is derived from the sequencing graph model under detailed timing constraints. Descriptions and analyses of these formulations are presented in subsequent chapters. 

This chapter is organized as follows. Section 4.1 describes the semantics of the sequencing graph model. Section 4.2 describes the derivation of a constraint graph model from a sequencing graph model under timing constraints. 

Section 4.3 describes the model of hardware resources used in synthesis. Section 4.4 summarizes the major features of the sequencing graph model. 

Table 4.1 Vertex types in the sequencing graph model representing HardwareC constructs.

In this section, we further separate the sequencing graph hierarchy into two forms calling hierarchy and control-flow hierarchy. 

Figure 4.4 The sequencing graph for the Greatest common divisor example, applies to call and loop vertices. Table 4.2 summarizes these properties.

---