D Placement

In a flattened design style, layout designers directly cany out the 2.5-D placement and routing tasks on a flatten netlist consisting of both standard cells and macros. Such a flow could usually accomplish superior solution quality, but at the cost of a longer turnaround time because of the inability to implement different blocks in parallel. 

The objective of the 2.5-D placement problem is to map a cell netlist (pure standard cell or mixed macro/standard cell) to unique positions in a layered space as illustrated in Fig. 6.1. The inter-chip contacts are assumed to be placed on top of the chip with no need to consume substrate area. We need to differentiate two scenarios hierarchical and flattened design styles. In a hierarchical design set up, after the floorplanning step, cells in a block need to be placed. As mentioned in the last chapter, a random-logic based block could be split into two chips. The 2.5-D placement problem is to assign the cells within such a block to unique positions on two chips. On the other hand, in a flattened design style, the 2.5-D placement problem is to place both standard cell macros onto stacked chips. 

In the following sections of this chapter, we studied the 2.5-D placement problem under the above mentioned three formulations pure standard cell designs with inter-chip contacts consuming substrate area, pure standard cell designs with inter-chip contacts on top of die surface, and mixed standard cell and macro designs corresponding to a flattened design style. 

In this section, we consider the second scenario of 2.5-D placement, where a hierarchical design style is applied and the inter-chip contacts can be placed above the top-level metal layer. 

D stack. We define such a space as a super-block. For the 2.5-D placement problem, a recursive partitioning procedure is carried out on the super-blocks. The process can be explained using the cube model illustrated in Fig. 6.2. For a... 

In our placement experiments, we assume a fixed-die, over-the-cell routing model. Thus, the layout area of a design is the footprint of all cells plus 10% free space. The 2-D layout is mapped to a 2.5-D layout consisting of two stacking chips with equal area. All layouts have a square shape. Thus, the dimension of two chips in 2.5-D system is that of the corresponding 2-D layout scaled by 0.707. For every benchmark circuit, we generate both monolithic (2-D) placement and 2.5-D placement. 

Total Wire Length Reduction ill 2.5-D Placement Worst-Case Wire Length Reduction in 2.5-D Placement... 

In the benchmarks listed in Table 6.4, the largest area percentage of total chip area occupied by a single macro is below 14%, which is relatively small. Therefore, we believe we can still use the top-down partitioning technique in the placement if we carefully control the cut line during partitioning. Unlike the case of standard cell placement, where we can use the available tool for the monolithic problem, now we have to build both monolithic and 2.5-D placement tools. Again we developed this tool on the basis of UCLA s Capo placer. 

Our 2.5-D placement tools could serve as the starting point to develop a full-fledged placement tools set for future 2.5-D/3-D ICs. Specifically, future... 

D placement tools have to be able to optimize multiple cost objectives in addition to the traditional wire length and critical path delay. 

D placement can be followed by a routability driven migration process so that the demand can be lowered by moving the least number of place-able objects. 

D placement tool has to generate solutions with a relatively even thermal map and low peak temperature. There has been a large body of work (e.g., [16,17]) proposed to solve the problem. For analytical based placers, the requirement for an even thermal can be formulated as a set of equations as constraints. On the other hand, under the context of partitioned based placement, a high power cell can be bloated to a certain extent so that it can be allocated with a larger white space and thus lower power density. 

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