D placement problem see colour plate

In the following sections of this chapter, we studied the 2.5-D placement problem under the above mentioned three formulations pure standard cell designs with inter-chip contacts consuming substrate area, pure standard cell designs with inter-chip contacts on top of die surface, and mixed standard cell and macro designs corresponding to a flattened design style. 

In this section, we consider the second scenario of 2.5-D placement, where a hierarchical design style is applied and the inter-chip contacts can be placed above the top-level metal layer. 

Bipartition Based Placement Input netlist N Output cell location cellLoc[] 

Variables Q = FIFO queue storing the subnetlists to be partitioned Subroutines  

Center(Ni) //return the center location of the layout area that contains subnetlist Ni Begin 

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