D placement process

During the vertical partitioning procedure, an essential issue is that the partition results should match the capacity of inter-chip communication resource. On one hand, the number of inter-chip contact on a given layout is determined by the interconnection technology. If the number of crossing-chip nets is beyond the 

Our standard cell benchmarks are from three sources Sun Micro s processor benchmark suite 10, UCLA Dragon benchmark suite 11and MCNC benchmarks 12. These benchmarks have very diverse functionalities and complexities. Sun Micro benchmarks listed in Table 6.1. A are typical CPU circuits such as integer unit, float-point unit, memory management unit, and large register file. They are delivered 

In our placement experiments, we assume a fixed-die, over-the-cell routing model. Thus, the layout area of a design is the footprint of all cells plus 10% free space. The 2-D layout is mapped to a 2.5-D layout consisting of two stacking chips with equal area. All layouts have a square shape. Thus, the dimension of two chips in 2.5-D system is that of the corresponding 2-D layout scaled by 0.707. For every benchmark circuit, we generate both monolithic (2-D) placement and 2.5-D placement. 

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