Cost per wafer

When considering a production reactor, we first assume that the requisite quality film can be made at least one at a time. The challenge then is to develop a reactor that is capable of acceptable wafer throughput with each wafer having film thickness within an acceptable tolerance. For example, we may want a reactor that can process 30 wafers per hour with thickness uniformity on a single wafer, and from wafer to wafer, of 5%. In addition, we may impose other conditions such as permissible number of particles per cm2, or for epi silicon films, the allowable number of defects per cm2. When we speak of wafer throughput, we are concerned with the actual cost per wafer for this process step. 

The cost per wafer will depend on many factors. First, the reactor can be quite expensive, so it is a capital item and must be amortized. Also, if the reactor has to be cleaned very frequently or is unreliable and experiences a lot of down time, then this will also add to the capital cost. If the reactants are expensive and not utilized efficiently, then this is another expense item. Energy requirements can be high for heating either the chamber or the susceptor. So, a system with high wafer throughput leads in the direction of lower cost per wafer, provided film quality is acceptable. 

Due to the high deposition rates possible at atmospheric pressure, approximately 1000 A/mtn, wafer throughput can be as high as 200 to 400 per hour. Also, since this is an atmospheric pressure reactor, there is no expensive vacuum system, and the capital cost of the reactor system is modest. These two facts contribute to a low cost per wafer processed, and has allowed this system to remain in commercial use for over 13 years. 

A new epi reactor, the "Precision Epi 7010," has recently been introduced by Applied Materials. The unusual layout of this new system is shown in Figure 14. The central concept in this new reactor system is lower processing cost per wafer, while hopefully maintaining the same quality of epi films. The design features that lower the per wafer cost are the dual susceptor design and the use of low-frequency induction for heating. With two susceptors, one can be loaded or unloaded while the other is being processed. 

In addition to the design goal of reducing the processing cost per wafer, this system has been developed to reduce the particulate contamination to a minimum. To accomplish this, the entire system is enclosed within a laminar flow hood, so that the wafers are handled in a class 10 environment. Secondly, wafers are loaded and unloaded by an automated robot, so that human intervention is not necessary to handle the two susceptors. Both of these features are illustrated in Figure 15. 

Having determined the mass transport for each reactant, it is possible to determine the process efficiency on a reactant by reactant basis. This, in turn, is important in determining operating costs or cost per wafer or device. The simplest and most direct measure of efficiency is the moles of epitaxial product produced, divided by the moles of reactant consumed. These numbers, in practice, are generally somewhat further distorted because the calculation is usually performed for the useful deposition plane,... 

The cost per CMP wafer pass is high when compared to other semiconductor manufacturing processes. This aspect of CMP reflects the rapid transfer of CMP into production, as well as the large amount of slurry and pads that are consumed during CMP. CMP CoO has improved in the last few years due to several factors. 

RGS wafers have the advantage of a more cost-effective fabrication due to the high-production speed. The expectation is that, even if the efficiency is somewhat lower, the introduction of RGS would further reduce the costs per Wp of PV modules. Improvements in wafer quality and an increased understanding of the interaction between defects and solar cell processing are necessary to reach higher efficiency values. 

The key factors driving the advancements in exposure tool technology are line width resolution, registration, and depth of focus. The ahdity to decrease device feature line width is heneficial in that it lowers cost, increases the number of dies produced per wafer, and also increases device speed. Registration helps to increase device yield and speed by accurately overlaying one layer on another. Depth of focus control helps to determine CD control and consequently device speed and yield. ... 

A full custom approach is selected to minimize the chip size or to implement a function that is not available or would not be optimum with semicustom or standard ICs. Minimizing chip size increases the fabrication yield and the number of chips per wafer. Both of these factors tend to reduce the cost per chip. 

Lowest cost per I/O because the interconnections are all done at the wafer level in one set of parallel steps... 

The first generation includes established technologies. Silicon-based systems make up around 90% of the current PV market and most are manufactured in Europe and Asia. The raw materials (silicon wafers) are expensive, shortages have had a massive impact on price, and high purity is required, therefore over half the cost is that of the silicon wafers. Nonetheless the cost per watt has decreased exponentially over the last few decades, leading to module retail prices of arormd 4.45 in the USA and 4.34 in Europe, due to increases in efficiency, which have now reached 23% for modules and 25% in the laboratory. ... 

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