Chips thermal mismatch stresses

For flip-chip solder joiiung, plastic strain of solder bumps is a critical parameter that governs the joint reliability. Increasing bump height can reduce the bump strain and thus increase the joint reliability, as shown in Fig. 15(a). However, a systematical study on the effect of bump height showed that the failure mechanism of ACA flip-chip joints is totally different (Ref 37). In ACA joints, the bump and pad are usually made of metals that are much stiffer than adhesives. In other words, thermal mismatch stresses can hardly deform the bump and pad, and the shear strain is localized in the adhesive between the mating bump and pad (Fig. 15b). In this case. 

A problem which arises when a read-out chip of for example silicon is attached to a detector chip of mercury cadmium telluride is the mechanical damage which may occur when the array is cooled to cryogenic temperatures for operation. The stress is due to a mismatch in the coefficients of thermal expansion between the two materials. 

Many fectors must be taken into consideration in designing an adhesive. The requirements include low level of ionic impurities, no voids under the chip caused by evaporation of solvent or other volatiles, no resin bleed during cure, and thermal expansion properties that match those of the substrate and chip. A significant mismatch in the thermal expansion coeflScient can lead to development of thermal stresses that can result in cracking or distortion of the chip. This problem is becoming more and more important as die sizes continue to increase. 

Lastly, adhesives are used to dissipate stresses that may be generated from thermal excursions, mechanical shock, vibration, or moisture. Specially formulated adhesives are effectively used as underfills for flip-chip devices and ball-grid-array packages to compensate for mismatches of expansion coefficients among the solder, the silicon chip, and the ceramic or plastic-laminate substrate. Low-stress adhesives are also used to attach fragile devices such glass diodes and to dampen stresses due to vibration. 

Radiation failures are principally caused by uranium and thorium contaminants and secondary cosmic rays. Radiation can cause wearout, aging, embrittlement of materials, or overstress soft errors in such electronic hardware as logic chips. Chemical failures occur in adverse chemical environments that result in corrosion, oxidation, or ionic surface dendritic growth. There may also be interactions between different types of stresses. For example, metal migration maybe accelerated in the presence of chemical contaminants and composition gradients and a thermal load can accelerate the failure mechanism due to a thermal expansion mismatch. 

Leaded vi. Leadless Surface-Mount Components. Leadless surface-mount components with peripheral solder joints (e.g., leadless ceramic chip carriers, LCCCs) are more susceptible to solder joint failures due to thermal and mechanical stresses than leaded components because there is no compliance in the system (see Fig. 57.21). A compliant lead can take up relative displacement between the component body and the substrate during mechanical or thermal stressing. In doing so, it minimizes the stress and strain imposed on the solder joint, thus reducing the likelihood of failures. Large leadless components should be avoided whenever possible. If they must be used, the substrate must have as close a CTE mismatch as possible and be protected from mechanical stresses. A conformal coating should be considered. 

A number of factors have enabled the economies in cost possible with the use of plastic packaged devices to be realised. The development of new grades with freedom from the ionisable impurities that could result in corrosion problems when transported to the chip surface by water permeation, the incorporation of corrosion inhibitors, the careful selection of plastic material (to avoid thermal expansion mismatches with resulting stresses on the chips) and the reduction in life expectancy of current equipment due to the rapid rate of development and outdaring of equipment associated with the new silicon technology has now resulted in plastic encapsulated devices dominating the component field. 

Lap shear test conditions are not really convenient in electronics involving small dice and two substrates with different thermal expansion coefficients (CTE). The stresses generated during the cure cycle by this CTE mismatch account for possible crack formation and delamination, which in turn may degrade the adhesive strength. The die shear strength method consists in the measurement of the force required to shear the die from the chip carrier. Although any die size can be used, a standard technique is to bond 1.27 X 1.27 mm non-functional silicon dice to silver-plated lead frames. 

Standard surface mount components do not require an underfill, however when assembling some CSPs onto organic PCBs, underfill may be required to increase the thermal and mechanical reliability of the interconnections. Some types of CSPs have a compliant elastomeric layer that decouples the chip-to-carrier body thermal expansion mismatch induced strains. That is the stresses exerted on the solder connections are dissipated by an elastomer that mechanically isolates the silicon die from its flexible polyimide film interposer. Those component designs which do not provide sufficient decoupling between die and carrier require an underfill to satisfy the reliability requirements for some applications. In addition, the components in hand-held consumer products are often underfilled to improve the mechanical robustness of an assemblies ability to withstand drop and shock resistance. Shock and impact requirements for CSPs in portable products may exceed 2,000 G accelerations. 

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