Integer adder

Figure 6.1 Integer adder using the built-in operator.

The synthesizer will always choose to implement an integer adder in this manner, regardless of the number of bits. As timing constraints for a particular design are not known at the synthesis stage, a circuit widi minimum area will be aimed for. Table 6.1 shows die statistics of this circuit. As... 

Table 6.1 Logic s)mthesis and optimization statistics for the integer adder and adder/subtractor architectures. Timing constraints were met in each case. No final area constraint was applied...

RIPPLE3 is a simpler architecture, although the function it calls is more flexible than the function called in RIPPLE I, for example. In this latest architecture, the ripple-cany function can add or subtract the 2 s complemented binary numbers. However, in this case it is called with a constant, (V. This means that the function will only ever be used for addition and so only the required elements of the function need to be s)mthesi2ed. The statistics in Table 6.2 show that the circuit produced is almost as small as the integer adder circuit. 

It is difficult to test for overflow in integer arithmetic. Unlike the user-defined functions created in this chapter tiie integer adder will simply discard any carry out or overflow bit. During simulation a warning is issued if overflow occurs but this is not synthesized into hardware. 

The blocking procedural assignment statement describes an adder that takes Preset and the integer 1 as inputs and places the result in the variable Count. 

The simplest version of an adder circuit is shown in Figure 6.1. This description does not introduce any new language elements but it is useful for later comparisons. Note that the input and output signals have predefined signed integer ranges. It is not usually sufficient to define the input ranges and let the outputs determine appropriate upper and lower botmds themselves. If ANSWER was left unconstrained it may use a 32-bit representation. This is synthesizer dependent and redundant outputs will be removed by area optimization. 

As before, the adder types are separated into three sections - Integer, RC and CLA Within each section both the s3mthesis and optimization results will be discussed together. 

The simplest adder, INTGR ADDER-ONEADD, demonstrated a signed integer addition operation. The circuit in Figure 6.14 shows how the simple addition operator is translated into hardware. The key features of this circuit include ... 

The same table shows the data for the INTGR ADDSUB-DATAFLOW model. This is an integer addition or subtraction circuit, the function of which is selected by the MODE input signal. As the statistics indicate, the s)mthesized circuit occupies almost three times the area as tiie single adder circuit. This consists of three elements ... 

ANSWER out INTEGER range -16 to 15 ) end INTGR ADDER OVER ... 

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