Wafer dielectric deposition

Apart from new low-dielectric materials, a clean method to deposit the dielectric as a uniform film is also required. Owing to the way fabrication technology in the microelectronics industry has developed and because larger silicon wafers (> 8 in.) are being used (currently, the technical difficulty of... 

The copyrolysis of 1 wt% dibromotetrafluoro-p-xylylene with commercially available hexafluoro-p-xylene (Aldrich) with metals was examined and it was found that it was indeed possible to prepare films that were spectroscopically indistinguishable from those deposited from dimer. The PA-F films obtained are of excellent quality, having dielectric constants of2.2-2.3 at 1 MHz and dissociation temperatures up to 530°C in N2. A uniformity of better than 10% can be routinely achieved with a 0.5-gm-thick film on a 5-in. silicon wafer with no measurable impurities as determined by XPS. During a typical deposition, the precursor was maintained at 50°C, the reaction zone (a ceramic tube packed with Cu or Ni) was kept at 375-550°C, and the substrate was cooled to -10 to -20°C. The deposited film had an atomic composition, C F 0 = 66 33 1 3 as determined by XPS. Except for 0, no impurities were detected. Within instrumental error, the film is stoichiometric. Poly(tetrafluoro-p-xylylene) has a theoretical composition ofC F = 2 1. Figure 18.2 illustrates the XPS ofthe binding energy... 

The selective Cu deposition process was suggested by Ting and Paunovic (13) as an alternative means of fabricating multilevel Cu interconnections (Fig. 19.4). The first step in this through-mask deposition process (14) is the deposition of a Cu seed layer on a Si wafer, and then a resist mask is deposited and patterned to expose the underlying seed layers in vias and trenches. In the next step, Cu is deposited to fill the pattern. After the Cu deposition mask is removed, the surrounding seed layer is etched and dielectric is deposited. Electroless Cu deposition has been suggested for the blanket and selective deposition processes (15). 

Bottom-gate, top-contact (Fig. 4.2a) and a bottom-gate, bottom-contact (Fig. 4.2b) TFT configurations are used to evaluate the FET performance of our semiconductors. The devices are built on an n-doped silicon wafer (gate electrode) with a 100-nm thermal silicon oxide (SiC>2) dielectric layer which is modified with a self-assembled monolayer of octyltrichlorosilane (OTS-8) to promote molecular ordering in the semiconductor layer. For the top-contact device the semiconductor layer ( 20-50 nm) is deposited on the OTS-8-modified SiC>2 surface by spin coating. A... 

The most commonly implemented and extensively investigated CMP steps are the preparation of planar premetal dielectrics (PMD) and interlayer dielectrics (ILD) films on wafer. Together they are labeled as oxide CMP, as they both use the same materials that are based on silicon dioxide. Both processes share the integration concerns in deposition, planarity, and defectivity. 

The liquid solution CCVD process does not deposit droplets (these evaporate in the flame environment) or powders as in traditional thermal spray processes. The CCVD technology is drastically different from spray pyrolysis In spray pyrolysis, a liquid mixture is sprayed onto a heated substrate, while CCVD atomizes a precursor solution into sub-micron droplets followed by vaporization of said droplets. The resulting coating capabilities and properties described hereafter qualifies CCVD as a true vapor deposition process. For example, depositions are not line-of-sight limited and achieve epitaxy, 10 nm dielectric coatings onto silicon wafers in a Class 100 clean room resulted... 

Additional work on dielectrics includes deposition of silica, PABS (lead aluminum boron silicates), PLZT (lead lanthanum zirconium titanate) and BST (barium strontium titanate) on Si-Ti-Pt wafers (Figure 2). The wafer specimens were patterned with metal electrodes and electronic properties were characterized. 

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