Wafer dicing

Fig. 6. (A) Photo of a chip with three cantilevers extended from the chip border. The photo has been taken before the wafer dicing. (B) An array of 20 cantilevers located in separate cavities. The cantilevers on both photographs were fabricated at the clean room facilities of CNM-IMB, Spain, from SOI wafers using the same technology.

MEMS devices need to be separated from the substrate using a wafer-dicing machine before they can be packaged. However, unlike IC devices, water used in the dicing operation will... 

Fig. 32.2 A typical process flow for integrated circuit (IC) fabrication. It is a complex process involving IC design and layout, circuit delineation on a semiconductor wafer, dicing of individual chips, appropriate packaging, and finally incorporating into the electronic product. (From Refs. 4 and 6.)...

The wafers are then sawn (or cleaved) into individual dice (- 250 x 250 ) and packaged (see Packaging Semiconductors and electronic... 

Silicon wafer grinding and dicing tapes used in electronic chip manufacturing. 

Another important factor is the corrosiveness of the adhesive. This may be especially important in those cases where the PSA has direct contact with the bare wire, the electronic component, or the silicon wafer in a dicing operation. In those cases where an electrical current is running through the device, electrolytic corrosion processes may occur, especially if moisture can penetrate into the adhesive or bond line. 

Here, it is easy to see the various layers and steps necessary to form the IC. We have already emphasized the formation of the n- and p-wells 8uid the individual proeess steps needed for their formation. Note that an epitaxial layer is used in the above model. There are isolation barriers present which we have already discussed. However, once the polysilicon gate transistors are formed, then metal Interconnects must then be placed in proper position with proper electrical isolation. This is the function of the dielectric layers put into place as succeeding layers on the IC dice. Once this is done, then the wafer is tested. 

Schematic of the Si-nMEA fabrication process (a) sputter Au layer on double-side polished wafer (b) pattern Au layer with liftoff process (c) spincoat and cure a polyimide layer (d) perform the double-sided photolithography to pattern etch pits (e) etch Si in ICP-DRIE to form Au/Si electrode (f) dice the wafer into a single die (g) RIE etch the polyimide layer with a shadow mask to expose current collecting region (h) electroplate Pt black on Au layer (i) sandwich both electrodes with Nafion 112 in a hot-press bonder. (Reprinted from J. Yeom et al. Sensors Actuators B107 (2005) 882-891. With permission from Elsevier.)...

The wafer is diced into pieces. Each piece is a small glass block with several cantilevers attached to its edges. 

Figure 1.11 is a simulation of randomly distributed micropipes, however, there is normally a tendency to cluster the micropipes, which would give somewhat better yields. Also, a significant amount of micropipes land in between the devices where the wafers are diced and these are considered harmless in the simulation. 

FIGURE 15.15 (a) Layout of dice and profilometry scans over a 200-mm wafer for wafer-level height distribution study, (b) Wafer-level height distribution for CMP over a nonideal die layout (four of the ten scan lines have been removed for clarity) (from Ref 114). 

The IC is fabricated by a series of lithographic processes similar to that described in the previous section. Each individual step constitutes a level in the device, the final level being a metalization pattern to interconnect the circuit elements that have been fiibricated in the surface of the silicon wafer. The completed wafer is then diced, a step that involves cutting the wafer, typically with a diamond saw, to separate the individual IC chips. The next step is to package the chips in some way, attach the devices along with other components to the printed wiring board (PWB), and interconnect them to produce the completed circuit board. 

Exposure of the photosensitive article. The exposure step photographically transfers a pattern from a reticle or photomask to the photoresist coated on the wafer surface. Photomasks are glass plates with patterns made of opaque and transparent areas. A photomask will typically have the pattern for a few dice and will be stepped across the wafer exposing the pattern after each step. In order to ease a task of a photomask fabrication and make the process less defect sensitive, photomask patterns are either 5x or 4x, the size of the desired feature on the wafer, and the photomask pattern is optically shrunk before reaching the wafer. 

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