Wafer bonding stacked devices

As indicated in the previous sections, CMP has found many applications in the manufacturing of More than Moore devices. In this chapter, examples will be discussed where polishing processes have to be employed for the manufacturing of power devices, MEMS and MOEMS chips, and micro-displays. The described applications are exemplary and do not claim completeness. Wafer bonding will be covered with examples from the fields of stacked devices and wafer-level packaging (WLP), while TSVs will be treated in more depth in a separate chapter in this book. 

Wafer bonding is a technology to combine two substrates in order to achieve a mechanically stable connection between them. The technology is apphed for substrate production, for example, for the fabrication of silicon on insulator wafers or compound semiconductor wafers and for device fabrication, for example, for the fabrication of MEMS/MOEMS devices as described in previous sections, for stacking devices in 3D integration, or for wafer-level packaging. 

Morrow P, Park C-M, Ramanathan S, Kobrinsky MJ, Harmes M. Three-dimensional wafer stacking via Cu-Cu bonding integrated with 65-nm strained-Si/ low- CMOS technology. IEEE Elect Device Lett 2006 27(5) 335-337. 

Once the epoxy bumps have been formed, the wafer is thinned from the backside, the devices are singulated, and their edges beveled at 45° to expose gold pads at the periphery of die. The chips are then stacked and bonded with thermally conductive, electrically insulative epoxy (Figure 5.16). Paste adhesives are cost effective and can be dispensed with existing epoxy dispensing equipment. However, with... 

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