Voltage stress

Tests on Cable Constructions. The Association of Edison Illumination Companies (AEIC) has approved an accelerated cable hfe test in which typical underground distribution power cables can be statistically compared based on their resistance to water treeing (number of days to fail). The comparison can be made by varying the type of insulation and/or other cable layers in an environment that contains hot water (90°C) under 8V/fi (200 V/mil) voltage stresses (four times the typical power cables operating voltages). 

While the transverse voltage stresses the main wall insulation, the longitudinal voltage stresses the interturn insulation. The bulk of the components of both... 

Higher voltage stresses, (equation (23.1)) may lead to dielectric breakdown. 

The significance of this term can be realized by the fact that the voltage stress of a surge, having a maximum amplitude of 4.5 p.u.. with a front time / of 5 ps. will roughly be the same or even less severe compared to a surge with an amplitude of only 2 p.u. and a front time of 0.2 ps (see Insulation Sub-committee. Rotating Machinery Committee, 1981). 

Figure 17.14 A transient voltage stress across the first (entrance) coil of an induction motor as a function of front time (/,) and length of entrance coil (from Slamecka, 1983)...

Finally, there seemed to be no pattern to the failures So we had to hook up a scope and current probe to check the 5 V diode waveforms to rule out excess current and voltage stresses. Note that a freewheeling diode failure will always precede a Fet failure, very rarely the other way around. In other words, if the diode failed, we would expect the Fet to fail soon thereafter, but if the Fet was what started it all, the diode would usually be found intact. So at least we were reasonably sure we were heading in the right direction by looking at the diode, not the Fet We looked at all the diode waveforms, and we were sure... 

It is important to get this calculation right if you are seriously worried about the efficiency of your Flyback. But don t forget to do a final bench verification—short and overload the output at high line, and capture the peak voltage stress on the Fet. 

Fig. 9.8. Deflection of a bimorph. Two long, thin plates of piezoelectric material are glued together, with a metal film sandwiched in between. Two more metal films cover the outer surfaces. Both piezoelectric plates are poled along the same direction, perpendicular to the large surface, labeled z. (A) By applying a voltage, stress of opposite sign is developed in both plates, which generates a torque. (B) The bimorph flexes to generate a stress to compensate the torque. The neutral plane, where the stress is zero, lies at hi i from the central plane.

In our discussion of SMPC circuits, the switching method has been assumed to be hard switching. In hard switching, the current and voltage stresses imposed on the switches and diodes are not considered (or minimized) by the control electronics. The duty cycle or frequency of the system is adjusted solely to maintain the required output voltage, current, or power. Switching losses in these systems can be quite high. 

ASTM D3755, 1997 (2004). Standard test method for dielectric breakdown voltage and dielectric strength of electrical insulating materials under direct voltage stress. 

The classical experimental setup developed for fe polarization reversal implies a singledomain fe sample sandwiched between two electrodes [28], While conventional domain inversion techniques use equal sized electrodes covering the polar faces of fe templates, nanodomain inversion occurs under totally different conditions when the bottom electrode is a uniform plate and the upper one is a point contact. Two different kinds of the upper switching mobile nanoelectrodes may be considered afm tip (and/or array of tips) and electron drop formed using electron beam exposure. When a voltage stress is applied to the nanoelectrode, both the electric field intensity and its spatial distribution strongly differ in fe thin films (thin fe crystals) and bulk fe crystals. 

Temperature (K) Thickness (cm) Volume resistivity (fi cm) Voltage stress at breakdown (kv/mm)... 

Figure 3. XPS spectra of a silicon sample containing ca. 30 nm thick oxide. A strip of gold metal is tied for referencing under different voltage stress. The inset displays the measured binding energy difference between the Si2p of the oxide layer (Si4+), and the Au4f of the gold metal. Zero Charge Point (ZCP) is obtained at ca. +1V stress.

By imposing a simple external voltage stress to the sample rod we have been able to control and measure the potential(s) developed as a result of charging in and on different layers/domains. This simple procedure is a powerful tool for enhancing peak separation. 

Figure 8. XPS spectra of the Si2p-Pt4f region of silicon sample containing ca. 6 nm thermal oxide layer, and also containing Pt particles deposited from an aqueous solution, and reduced by x-rays without and under +10 and -10V external voltage stress. The figure also contains spectra recorded with 0 to +10V pulses at 50, and 0.5 Hz, 0 to -10V pulses again at 50 and 0.5 Hz.

Prior to the physical analysis by the TEM, the electrical behavior of the dielectric layer is routinely characterized and then stressed to induce a breakdown using the standard constant voltage stress methodology [9]. However, in order to ensure that the dielectric breakdown spot has a high probability of being captured in the TEM samples, the width, i.e., W, of about 0.4 pm or less of the transistor shown in Fig. 1 has to be selected [10-14]. 

---