Trench filling isolation

To achieve the lowest possible delay a bipolar switching transistor developed by IBM minimizes parasitic resistances and capacitances. It consists of self-aligned emitter and base contacts, a thin intrinsic base with an optimized collector doping profile, and deep-trench isolation (36). Devices must be isolated from each other to prevent unwanted interactions in integrated circuits. While p—n junctions can be used for isolation, IBM s approach etches deep trenches in the siUcon wafer which are filled with Si02 to provide electrical insulation. 

MOSFETT s, and silicon oxide is deposited. The source/drain positions where electrical contact is to be made to the MOSFETs are defined, using the oxide-removal mask and an etch process. For shallow trench isolation, anisotropic silicon etch, thermal oxidation, oxide fill and chemical mechanical leveling are the processes employed. For shallow source/drains formation, ion implantation techniques are still be used. For raised source/drains (as shown in the above diagram) cobalt silicide is being used instead of Ti/TLN silicides. Cobalt metal is deposited and reacted by a rapid thermal treatment to form the silicide. Capacitors were made in 1997 from various oxides and nitrides. The use of tantalmn pentoxide in 1999 has proven superior. Platinum is used as the plate material. 

A key benefit of accurate CMP models that needs emphasis is the capability to optimize layout design before polishing. Post-CMP ILD thickness variation is a serious concern from both functionality and reliability concerns. An effective method of minimizing this effect is the use of dummy fill patterns that lead to a more equitable pattern density distribution across the chip. Evaluation of such schemes before actual product implementation has become a major use of CMP modeling [53]. Dummy fill is also being investigated for front-end processes where shallow trench isolation CMP suffers from substantial pattern dependencies. 

With this optimization technique, topography is reduced after the planarization step. The STI trenches are filled with polysilicon instead of Si02 [39]. After trench, etching, the first patterned hard mask is stripped and a new continuous oxide/nitride layer is deposited for electrical isolation between the substrate and the trench polysilicon. After CMP, the dishing in isolation areas is counteracted by a high-temperature oxidation step, which oxidizes the upper part of the remaining polysilicon in the trenches. As the volume of the Si02 is... 

Nag S, Chatterjee A, Taylor K, Ali I, O Brien S, Aur S, Luttmer J, Chen I-C. Comparative evaluation of gap-fill dielectrics in shallow trench isolation for sub-0.25 pm technologies. lEDM Technical Digest Dec 1996. p 841-844. 

Lee HS, Park MH, Shin YG, Park T-S, Kang HK, Lee SI, Lee MY. An optimized densification of the filled oxide for quarter micron shallow trench isolation (STl). S5mposium on VLSI Technology Technical Digest June 1996. p 158-157. 

Following the STI etch operation, the wafer is again cleaned to remove contamination and surface oxide, after which it undergoes a high-temperature oxidation in a furnace in the presence of oxygen. This results in the growth of a thin layer of silicon dioxide (called the liner oxide) in the exposed walls of the isolation trenches. The liner oxide serves to improve the interface between the silicon and the trench CVD oxide that will be subsequently deposited. The trench is then filled with CVD oxide (see Fig. 16.8). 

Optimum device isolation is not only restricted to the deep trench isolation between devices, but also calls for shallow trenches to allow isolation between the base and the subcollector reach-through diffusion. This trench reaches down to the subcollector only. A third trench shape option is that of wide, deep trenches. These would be formed outside of the immediate device areas and serve (after filling with SiO ) as the bed on which to locate the wiring lines which interconnect the different devices and circuits. Locating wires on such SiO2 areas reduces the wiring capacitances significantly. 

In the case of device applications, the filling material is some form of dielectric material, such as oxides, polymers, or polycrystalline silicon. (Metal filled trenches could serve as buried interconnecting device lines). As suggested previously, generally two types of trenches may have to be filled up - narrow ones for device isolation, and wider ones to benefit other circuit functions. The process requirements are somewhat different for each. However, independent of the trench width, the initial processing is the same. 

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