Through-wafer etch

Fabricating waveguides on the surface of a wafer provides ready access to fluidic channels without the need for through-wafer etching as required in a wafer... 

Kumar, S. and Pike, W.T. (2005) Technique for eliminating notching in through-wafer etching. 16th MME Micromechanics Eur. Workshop P15, 8 8-91... 

Plasma Etching, Fig. 6 Cross-sectional SEM micrographs of (a) high aspect ratio microstructure of holes with the same nominal diameter of 1.5 pm and nearly the same etching depth of 69.5 pm, (b) through-wafer etching... 

Figure 1.13 Patterned SOIMUMPS wafer. Through-wafer etches are performed from the front side of the wafer 10 or 25 pm deep to form device layer holes, and from the back side 400 pm deep to form through-wafer holes.

Figure 8.10 Through-wafer etch holes to enable back-side release. The backside etch holes eliminate the need for etch holes in the Poly2 mirror membrane. (Reprinted with permission from IEEE Journal of Selected Topics in Quantum Electronics, Microelectromechanical deformable mirrors, 1967 IEEE.)...

An important component in the process flow is a through-wafer via with a nitride liner (and metal fill) that can act as an etch stop for the grinding and polishing wafer-thinning step. This capability allows uniform thinned layers and could provide good wafer-scale planarity for subsequent processing (although characterization of wafer-level planarization has not been reported to date) [41]. Available product information describes the performance and specifications of 3D components [40,42]. 

Chambers A, Ashraf H, Hopkins J, Pink J. Through-wafer via etching. Advanced Packaging April 2005. p 16-20. 

Samalam [43] modeled the convective heat transfer in water flowing through microchannels etched in the back of silicon wafers. The problem was reduced to a quasi-two dimensional non-linear differential equation under certain reasonably simplified and physically justifiable conditions, and was solved exactly. The optimum channel dimensions (width and spacing) were obtained analytically for a low thermal resistance. The calculations show that optimizing the channel dimensions for low aspect ratio channels is much more important than for large aspect ratios. However, a crucial approximation that the fluid thermophysical properties are independent of temperature was made, which could be a source of considerable error, especially in microchannels with heat transfer. 

The substrate is 425 tm thick (see Note 5). The cantilevers were fabricated in separate cavities with a pitch of 250 tm between them. The cavities are the through-wafer holes drilled using a deep reactive ion etching (DRIE) technique. Each cantilever was 40 pm wide and 200 pm long, the thickness of each cantilever was 334nm (which was fixed by the thickness of the structural layer) (see Note 6). 

Two top-down strategies have been developed for the production of pSi. The most widely used strategy is electrochemical etch, while the other approach, stain etch, is rarely used in practice due to its severe lack of flexibility [19]. The most widely employed top-down approach produces pSi through electrochemical etch of a bulk siUcon wafer. The pSi can then be oxidized to take advantage of silane chemistry. Alternatively, its surface can be carbon-terminated to obtain a hydrophilic chemically stable interface [20]. 

Step 12 Etch through Si wafer using Ki until the ntetal film is exposed... 

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