Thin film multilayer interconnects

Copper/Polyimide Thin Film Multilayer Interconnect Structure... 

Figure 16. Cross section of thin-film multilayer interconnections on a pinned cofired ceramic substrate, with face-up tape-automated-bonded chip and thermal vias. (Reproduced with permission from reference 79. Copyright 1988 Materials Research Society.)...

Material Options for Thin-Film Multilayer Interconnections... 

A typical polyimide (BDTA-ODA-MPD) for thin-film multilayer interconnections... 

Figure 1. Proposed approach for multichip packaging using thin film multilayer Cu/polyimide interconnections.

With advancements in MCMs, where large chips (up to 500-mils square) are closely packed and where devices and interconnect substrates are fragile (for example, polyimide thin-film multilayer substrates used in MCM-D), new rework challenges have arisen. In these high-density circuits, spacings between the chips may be as small as 40 mils—too small... 

In all but the simplest electronic circuits, it is necessary to have a method for fabricating multilayer interconnection structures to enable all the necessary points to be connected. The thick film technology is limited to three layers for all practical purposes because of yield and planarity considerations, and thin-film multilayer circuits are quite expensive to fabricate. The copper technologies can produce only a single layer because of processing limitations. 

A detector mosaic which is bonded to a multilayer alternating thick film and thin film interconnect pattern is disclosed in EP-A-0281026. 

Each detector 14 includes a detector crystal region 21 having a junction 22 which is connected to an indium bump 23. The indium bump bonds to the bonding pad 80 which is, in turn, bonded to a metallized trace 13. The sensitive area plane 12 is parallel to the plane formed by the edge of the supporting substrate and the multilayer thick/thin film interconnect pattern 50. 

PBO and PBZT films can be made very thin (less than 0.002 in.) and can be impregnated with secondary resins, resulting in a substrate with a dielectric constant less than 2.8, an isotropic planar CTE of 7 ppm per °C or less, and temperature resistance over 250°C. Copper circuits and ground planes can be added by a variety of additive or substrative means, and multilayer circuit boards can be fabricated using plated through holes. Further development of these thin film dielectric substrates should result in interconnection density over 100 times greater than is currently possible with fiber reinforced epoxy multilayer boards. 

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