Thermal oxide etching

Plasma etching was performed on polymer films coated on 6-inch silicon wafers to a thickness of 150 to 200 nm. Thermal oxide etching was performed... 

Time to Plasma Strip a 0.4 O.D. Film Thermal Oxide Etch... 

Fig. 4 shows the SEM images of SWNTs purified by the thermal oxidation and acid-treated. Fig. 4(a) shows a SEM image of the raw soot. In addition to the bundle of SWNTs, carbonaceous particles are shown in the figure. These stractural features mi t be causal by various in the arcing process because of an inhomogeneous distribution of catalysts in the anodes [7]. It can be seen that the appearance of SWNTs was curled and quite different fiom that of MWNTs. Fig. 4(b) shows a decrease of amorphous carbons after oxidation. The basic idea of the selective etching is that amorphous carbons can be etched away more easily than SWNTs due to the faster oxidation reaction rate [2]. Since the CNTs are etched away at the same time, the yield is usually low. The transition metals can be etched away by an add treatment. Fig. 4(c) shows the SEM image of the acid-treated sample, where the annealed sample was immersed in 10 % HCl. 

MOSFETT s, and silicon oxide is deposited. The source/drain positions where electrical contact is to be made to the MOSFETs are defined, using the oxide-removal mask and an etch process. For shallow trench isolation, anisotropic silicon etch, thermal oxidation, oxide fill and chemical mechanical leveling are the processes employed. For shallow source/drains formation, ion implantation techniques are still be used. For raised source/drains (as shown in the above diagram) cobalt silicide is being used instead of Ti/TLN silicides. Cobalt metal is deposited and reacted by a rapid thermal treatment to form the silicide. Capacitors were made in 1997 from various oxides and nitrides. The use of tantalmn pentoxide in 1999 has proven superior. Platinum is used as the plate material. 

Fig. 2.8 Etch rate of thermal oxide and CVD nitride (deposited at 850 °C) as a function of aqueous HF concentration at RT.

Etch rates in nm s I Thermal oxide CVD- nitride Undoped poly-Si Bulk Si (100) Aluminum... 

Figure 26, A comparison of the etch rates of thermal oxide, acrylate resist (PMMA) and AZ resist using DE-100 gas at 200W and 0,55 Torr, The shaded areas surrounding the acrylate and AZ curves represent the etch rates of typical aliphatic and aromatic polymers respectively.

High etch rates and selectivity can be achieved by judicious selection of feed gases to a plasma reactor. The atomic and radical species formed by electron impact dissociation depend largely on feed gas composition, and the intrinsic etch rates measured in the absence of a plasma (i.e., downstream etching) provide a useful indicator of chemical selectivity in the presence of a plasma. For example, the ratio of (100) silicon (34) to thermal oxide (Si02) (37) etching by F atoms is 41 1 at room temperature. As etch rates generally follow an Arrhenius type dependence on substrate temperature. 

The SiC Schottky diodes and capacitors that have been processed by the authors were processed on either 6H or 4H substrates (n-type, about 1 x 10 cm ) with a 5-10- m n-type epilayer (2-6 x lO cm" ) [123, 124]. A thermal oxide was grown and holes were etched for the metal contacts. In the case of the Schottky sensors, the SiC surface was exposed to ozone for 10 minutes before deposition of the contact metal. This ozone treatment produces a native silicon dioxide of 10 1 A, as measured by ellipsometry [74, 75]. The MISiC-FET sensors (Figure 2.9) were processed on 4H-SiC, as previously described [125]. The catalytic metal contacts consisted of 10-nm TaSiyiOO-nm Pt, porous Pt, or porous Ir deposited by sputtering or by e-gun. 

Oxide layers of various thickness (260, 182, 98, 62, 43, or 20 A) were prepared on the Si wafers. At the beginning we prepared an oxide layer thicker than 200 A by thermal oxidation, and then evaluated the thickness (260 A). Following that, the 260-A thick layer was etched down to each thickness using a 1.6%-HF aqueous solution. Each thickness was evaluated with an ellipsometer. Using Auger electron spectroscopy, we determined the thickness of the native oxide layer on the Si wafer to be 11 A. 

Xie et al. [20] reported the fabrication chip for pumps and an electrospray nozzle. The process used to fabricate the electrochemical pump chips with electrospray nozzle is shown in Fig. 2.11. A 1.5 xm layer of Si02 was grown on the surface of a 4 inch silicon wafer by thermal oxidation. The front side oxide layer was patterned and removed with buffered FIF. XeF2 gaseous etching was used to roughen the silicon surface in order to promote the adhesion between subsequent layers and the substrate. The first 4.5 p,m parylene layer was deposited. 

The micro channel system was fabricated by standard silicon micromachining via etching of a silicon wafer with potassium hydroxide using thermal oxide as an etch mask [6], The double mixing tee configuration consists of six micro channels. For fluid connection, an outlet hole was drilled into the silicon chip. The chip was anodically bonded to a glass slide with three inlet holes, clamped in a holder and, thereby, connected to a commercially available quench-flow instrument... 

Further investigation of the nature of these films4 has shown that there is about 2.7% Cl remaining in the completed film. Upon exposing them to a thermal oxidation environment, it was discovered that the interface between the oxide and silicon was etched and film adhesion was lost—the films flaked off. Apparently, the thermal oxidation process released bound chlorine in the oxide which then diffused to the interface where it attacked the silicon. 

Si02 Buffert hydrofluoric acid, RIE Dry etching, deep reactive ion etching DRIE Thermische thermal oxidation, low-pressure chemical vapor deposition Crystallographic and wet chemical etching of silicon... 

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