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Surface states Fermi level pinning

The degree of surface cleanliness or even ordering can be determined by REELS, especially from the intense VEELS signals. The relative intensity of the surface and bulk plasmon peaks is often more sensitive to surface contamination than AES, especially for elements like Al, which have intense plasmon peaks. Semiconductor surfaces often have surface states due to dangling bonds that are unique to each crystal orientation, which have been used in the case of Si and GaAs to follow in situ the formation of metal contacts and to resolve such issues as Fermi-level pinning and its role in Schottky barrier heights. [Pg.328]

In the absence of either surface states, which may pin the Fermi level at the interface between the dielectric and the electrode, the energy barriers, which in turn... [Pg.196]

Manipulating surface states of semiconductors for energy conversion applications is one problem area common to electronic devices as well. The problem of Fermi level pinning by surface states with GaAs, for example, raises difficulties in the development of field effect transistors that depend on the... [Pg.69]

The conclusions from these considerations are that semiconductor photoelectrodes can be used to effect either reductions (p-type semiconductors) or oxidations (n-type semiconductors) in an uphill fashion. The extent to which reaction can be driven uphill, Ey, is no greater than Eg, but may be lower than Eg owing to surface states between Eqb and Eye or to an Inappropriate value of Ere(jox. Both Eg and Epg are properties that depend on the semiconductor bulk and surface properties. Interestingly, Ey can be independent of Ere(jox meaning that the choice of Ere(jox and the associated redox reagents can be made on the basis of factors other than theoretical efficiency, for a given semiconductor. Thus, the important reduction processes represented by the half-reactions (3)-(5) could, in principle, be effected with the same efficiency at a Fermi level pinned (or... [Pg.70]

In cases in which the surface state density is high Nc/i,Nm, Ny/i,Nm - 1), electron distribution in the siuface state conforms to the Fermi function (the state of degeneracy) and the Fermi level is pinned at the surface state level. This is what is called the Fermi level pinning at the surface state. [Pg.42]

Fig. 2-81. Surface degeneracy caused by Fermi level pinning at a surface state of high state density (a) in flat band state (Ep ep), G>) in electron equilibrium (cp = cp). cp = surface Fermi level = surface ccmduction band edge level. Fig. 2-81. Surface degeneracy caused by Fermi level pinning at a surface state of high state density (a) in flat band state (Ep ep), G>) in electron equilibrium (cp = cp). cp = surface Fermi level = surface ccmduction band edge level.
Since the electron state density near the Fermi level at the degenerated surface (Fermi level pinning) is so high as to be comparable with that of metals, the Fermi level pinning at the surface state, at the conduction band, or at the valence band, is often called the quasi-metallization of semiconductor surfaces. As is described in Chap. 8, the quasi-metallized surface occasionally plays an important role in semiconductor electrode reactions. [Pg.44]

Simple calculation gives a comparable distribution of the electrode potential in the two layers, (64< >h/64( sc) = 1 at the surface state density of about 10cm" that is about one percent of the smface atoms of semiconductors. Figure 5—40 shows the distribution of the electrode potential in the two layers as a function of the surface state density. At a surface state density greater than one percent of the surface atom density, almost all the change of electrode potential occurs in the compact layer, (6A /5d )>l, in the same way as occurs with metal electrodes. Such a state of the semiconductor electrode is called the quasi-metallic state or quasi-metallization of the interface of semiconductor electrodes, which is described in Sec. 5.9 as Fermi level pinning at the surface state of semiconductor electrodes. [Pg.171]

Fig. S-41. Band edge levels and Fermi level of semiconductor electrode (A) band edge level pinning, (a) flat band electrode, (b) under cathodic polarization, (c) under anodic polarization (B) Fermi level pinning, (d) initial electrode, (e) under cathodic polarization, (f) imder anodic polarization, ep = Fermi level = conduction band edge level at an interface Ev = valence band edge level at an interface e = surface state level = potential across a compact layer. Fig. S-41. Band edge levels and Fermi level of semiconductor electrode (A) band edge level pinning, (a) flat band electrode, (b) under cathodic polarization, (c) under anodic polarization (B) Fermi level pinning, (d) initial electrode, (e) under cathodic polarization, (f) imder anodic polarization, ep = Fermi level = conduction band edge level at an interface Ev = valence band edge level at an interface e = surface state level = potential across a compact layer.
In the state of Fermi level pinning, the Fermi level at the interface is at the surface state level both where the level density is high and where the electron level is in the state of degeneracy similar to an allowed band level for electrons in metals. The Fermi level pinning is thus regarded as quasi-metallization of the interface of semiconductor electrodes, making semiconductor electrodes behave like metal electrodes at which all the change of electrode potential occurs in the compact layer. [Pg.174]

The surface state capacity, Ch, is apparently zero in the range of potential where the Fermi level is located away from the surface state level (the state of band edge level pinning). As the Fermi level is pinned at the surface state, the capacity Ch increases to its maximum which is equivalent to the capacity Ch of the compact layer, because the surface state charging is equivalent to the compact layer charging in the state of Fermi level pinning. [Pg.191]

In the state of band edge level pinning where all the change in electrode potential occurs in the space diarge layer, Mec, the anodic polarization curve of the oxidative dissolution follows Eqn. 9-53. As anodic polarization increases, the electrode interface enters a state of Fermi level pinning, in which all the change in electrode potential occurs in the compact layer, A ir, and the concentration of surface cations in Eqns. 9-54 then decreases with increasrng anodic polarization. [Pg.311]

A drastic decrease of photovoltage in UHV is obtained by introduction of surface states at the semiconductor surface. Particle bombardement of cleaved (0001) faces leads to preferential sputtering of the chalcogenide. The metal is reduced and new electronic bandgap states are formed at the surface. As a consequence a Fermi level pinning effect occurs which results in a smaller shift of EB due to halogen adsorption and decreased photovoltages and consequently an increased double layer potential drop (Fig. 4). [Pg.129]

The surface concentration of electrons depends on the potential drop (band bending) in the semiconductor, and in the absence of complications due to surface state charging (Fermi level pinning), it is given by (cf. equation (8.5))... [Pg.238]

Finally, interface states, that is, electronic states localized at the interface, are always present in the case of semiconductors and may be very important in fixing the Fermi level at the interface (Fermi level pinning) and modify the barrier height. In the case of organic solids in general, and of CPs, the existence of a surface does not imply that of dangling (i.e.,... [Pg.607]

At higher densities of surface states, it may be expected that the emptying and filling of surface states will cause a significant change in the potential within the depletion layer. Provided the dominant kinetics are those between surface state and semiconductor interior, we may then analyse the situation as a case II Fermi-level pinning problem. The total potential dropped in the interfacial region... [Pg.114]

C Elimination of Surface States, and Fermi Level Pinning... [Pg.243]

Fermi level pinning the ability of surface states to buffer the Fermi level of the semiconductor from changes in the electrochemical potential of the contacting phase Forward bias the sign of the applied potential that results in an exponential increase in the current passing through a semiconductor junction... [Pg.4341]

Quantitative calculations of the number of surface states that are needed to achieve Fermi level pinning will not be described here. However, such calculations show that even surface state densities as low as 10% of a monolayer (10 states cm ) can provide sufficient charge to induce complete... [Pg.4350]

Lower surface state densities will, of course, produce less of a Fermi level pinning effect. This will result in an increased sensitivity of Vbi to changes in A quantitative measure of the degree of ideality of a junction can be obtained by plotting changes in Vpi (or [Pg.4351]

Bard et al. have emphasized that there may be exceptions in so far as Fermi level-pinning by surface states may occur similarly as at semiconductor-metal junctions [62]. Such an effect would lead to an unpinning of bands. There are some examples in the literature, such as FeS2 in aqueous solutions [63,64] and Si in CH3OH [65], for which an unpinning of bands has been reported. In some cases, the interpretation is based on investigations of photocurrents, which will be discussed in the next section. [Pg.122]

Cao et al. reported an alternative Fermi-level pinning model to rationalize the potential distribution at negative applied potentials [147]. They suggested that the reduction of Ti surface states to TF , observed by low-temperature EPR spectroscopy, pins the Fermi level and, as the potential is raised further, the potential drops across the solution-semiconductor interface. [Pg.2759]


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See also in sourсe #XX -- [ Pg.206 ]




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Fermi level

Fermi level pinning

Fermi level pinning state

Fermi levell

Fermi pinning

Level surface

Pin, pins

Pinning

Surface Fermi

Surface Fermi level

Surface leveling

Surface pinning

Surface states

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