Spike sorting

Following [52], the Classification Mattix is used to quantify the performance of spike sorting algorithms. It is defined as... 

Fig. 47 Block diagram of an on-line spike sorting engine...

The IC was fabricated in a 0.35-p,m 4M2P CMOS process and the chip size is 8.8 X 7.2 mm (Fig. 50). The measured power consumption of the entire chip is 6 mW from 1.65 V when operating in streaming mode. The 8 front-end blocks consume 50% of the total power. The UWB TX consumes 1.6 mW with PPM modulation. The power consumption of the DSP block is only 0.1 mW. Waveforms at the output of amplifier, spike sorting, UWB TX, and UWB RX were monitored by the built-in test circuits (Fig. 51). 

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