Silicon planar technology

GaAs, CdTe and HgCdTe are deposited epitaxially on a silicon substrate in US-A-4910154. If islands of individual detector elements are formed, the deposited layers will have a combined thickness which makes it difficult to interconnect the detector elements with corresponding silicon circuitry due to the steep sides of the detector elements. It is therefore proposed to grow the GaAs, CdTe and HgCdTe layers in recesses formed in the silicon substrate, and interconnect with a planar technology. 

Arsenosilicates (AsSG) were employed originally in silicon device technology as an arsenic dopant source for planar substrates prior to the advent of large scale ion... 

Wafer processing is often called planar processing or planar technology because small and thin planar structures are built on thin wafers 500 pm thick) of ultra pure silicon or germanium or any other suitable semi-conductor material. The thin wafers are cut from a rod of pure material, which is a single crystal, and then polished. The structures built on the surface of the wafer are electrical components such as resistors, capacitors, diodes, junction transistors, MOSFET transistors, etc. Each wafer contains 200 to 500 chips, with each chip identical to the others. 

Metal silicides are sometimes regarded as intermetallics even if silicon is not strictly speaking a metal. They are quite useful in metallurgy and are applied in planar technology in electronics as metallic conductors to make contact with the silicon semiconductor. Some silicide structures are shown in Figure 4.31. 

A novel method of planar polarisation interferometry (PPI) [14, 15] was adopted here for monitoring the immune reaction with enhanced sensitivity. Planar waveguides, schematically shown in Fig. 5a, were fabricated by planar technology on silicon wafers and consists of 1.3 pm thick layer of Si02,190 nm thick Si3N4 layer and 1pm thick layer of phosphorosilicate glass. 

According to our experimental results [37], selectivity may be achieved by gas-phase catalyst delivery [38 0] on lithographically machined planar and nonplanar templates consisting of oxidized silicon surfaces. Our bottom-up fabrication approach is easy to carry out, scalable to large areas, and compatible with standard silicon microfabrication technology. In this specific CVD process, nanotube structures are designed and built first on planar patterns composed of SiOa and Si most of the substrates used in this study were Si(lOO) wafers capped with a lOO-nm-thick silica layer, however, below we discuss the case of thick silica layers (up to 8.5 M-m). 

Brown, D. M., et al., High Temperature Silicon Carbide Planar IC Technology and First Monolithic SiC Operational Amplifier IC, Trans, of 2nd Inti. High-Temp. Elec. Conf. (HiTEC), 1994, pp. XI-17-XI-22. 

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