Silicon oxidation oxide layer

Distance liquid and gas ports 3 mm Silicon oxide layer thickness 200-500 pm... 

A cross-sectional schematic of a monolithic gas sensor system featuring a microhotplate is shown in Fig. 2.2. Its fabrication relies on an industrial CMOS-process with subsequent micromachining steps. Diverse thin-film layers, which can be used for electrical insulation and passivation, are available in the CMOS-process. They are denoted dielectric layers and include several silicon-oxide layers such as the thermal field oxide, the contact oxide and the intermetal oxide as well as a silicon-nitride layer that serves as passivation. All these materials exhibit a characteristically low thermal conductivity, so that a membrane, which consists of only the dielectric layers, provides excellent thermal insulation between the bulk-silicon chip and a heated area. The heated area features a resistive heater, a temperature sensor, and the electrodes that contact the deposited sensitive metal oxide. An additional temperature sensor is integrated close to the circuitry on the bulk chip to monitor the overall chip temperature. The membrane is released by etching away the silicon underneath the dielectric layers. Depending on the micromachining procedure, it is possible to leave a silicon island underneath the heated area. Such an island can serve as a heat spreader and also mechanically stabihzes the membrane. The fabrication process will be explained in more detail in Chap 4. 

During the last 5 years, there have been several reports of multiblock copolymer brushes by the grafting-from method. The most common substrates are gold and silicon oxide layers but there have been reports of diblock brush formation on clay surfaces [37] and silicon-hydride surfaces [38]. Most of the newer reports have utilized ATRP [34,38-43] but there have been a couple of reports that utilized anionic polymerization [44, 45]. Zhao and co-workers [21,22] have used a combination of ATRP and nitroxide-mediated polymerization to prepare mixed poly(methyl methacrylate) (PMMA)Zpolystyrene (PS) brushes from a difunctional initiator. These Y-shaped brushes could be considered block copolymers that are surface immobilized at the block junction. 

Fig. 16. Influence of the ionic strength in the prevention of readhesion phenomenon in the case of a positive particle on a negative substrate (alumina slurries on silicon oxide layer) a high-ionic-strength limit the double layer thickness. Particle and substrate are therefore electrically masked at a closer particle-substrate distance. (The double layer of the substrate is not represented here.)...

Fig. 13.20. Optical heterodyne force microscopy (OHFM) and its application to a copper strip of width 500 nm, thickness 350 nm, on a silicon substrate, with subsequent chemical vapour deposition (CVD) of a silicon oxide layer followed by polishing and evaporation of a chromium layer of uniform thickness 100 nm and flatness better than 10 nm (a) amplitude (b) phase 2.5 [im x 2.5 m. Ultrasonic vibration at fi = 4.190 MHz was applied to the cantilever light of wavelength 830 nm was chopped at fo = 4.193 MHz and focused through the tip to a spot of diameter 2 im with incident mean power 0.5 mW the cantilever resonant frequency was 38 kHz. The non-linear tip-sample interaction generates vibrations of the cantilever at the difference frequency f2 — f = 3 kHz (Tomoda et al. 2003).

CVD processing can be used to provide selective deposition on certain areas of a surface. Selective tungsten CVD is used to fill vias or holes selectively through silicon oxide layers in silicon-device technology. In this case, the silicon from the substrate catalyzes the reduction of tungsten hexafluoride, whereas the silicon oxide does not. Selective CVD deposition can also be accomplished using lasers or focused electron beams for local heating. 

By placing vacuum at the exit of the reactor the catalyst particle could be unloaded, and using the inert gas stream at the inlet of the reactor, new catalyst can be placed. At the outlet of the reaction channel two posts 25 pm apart act as a filter to retain the catalyst particles. In addition, some channels were used to hold thermocouples or optical fibers to monitor the experimental conditions. To prevent corrosion of silicon by gaseous chlorine, the channels are covered with a silicon oxide layer of about 5 nm thickness. The reactor is capped with a Pyrex wafer [39]. A more detailed description of the reactor is given in [61]. 

In a second embodiment the strip detectors A to H are mounted on an intrinsic p-type silicon substrate 3A covered by a silicon oxide layer 3B. A patterned arrangement of conductor tracks 21 is formed in the semiconductor base 3B. Each track is formed by diffusion or ion-implantation of an n-type dopant material, and isolated from adjacent tracks by means of a channel stop network 23. Bridging links of nichrome-gold are formed to define and connect the read-out regions to the tracks 21. The links 25 are paired and thus provide voltage detection contacts. The tracks 21 are connected to connection pads 29. Signal processing circuitry is incorporated in the semiconductor base layer 3B. 

An CCD read-out circuit having p-type input regions 2 is formed in an n-type silicon substrate 1. A silicon oxide layer 4 is formed and openings corresponding to the input regions are provided. Metal electrodes 3 are formed by vapor deposition to connect to the input regions. A... 

Figure 1. Part of the XPS spectrum showing the Si2p-Au4f peaks of a silicon substrate containing ca. 4 nm thermal oxide layer with one drop of 0.0001 M aqueous solution of HAuCL deposited, and dried in air. The silicon peaks corresponding to the silicon substrate (Si0) and the silicon oxide layer (Si4+), as well as two different chemical state of gold (Au3+ and Au°) are clearly resolved.

The more important observation is that the measured difference between the twinned peaks of the Si4+, the Si0, and the Pt° display different functional behavior with respect to frequency. The silicon oxide layer shifts the most, the silicon substrate in the middle, and the platinum species least. Measured binding energies can change several eV, depending on parameters like particle... 

In order to remove the resist after the RIE treatment, wafers were immersed in phenolic-type resist stripper, but the resist as well as the scum could not be stripped. Since a thin silicon oxide layer is formed on the resist surface, and the composition of scum is thought to be silicon oxide as discussed above, it is necessary to remove this silicon oxide layer (scum) prior to the resist removal. Therefore, resist stripping was done in two steps. In a first step the wafer was immersed in buffered hydrofluoric acid solution to remove the silicon oxide and was then treated with conventional resist stripper. 

We have studied alternating germanium-silicon-silicon oxide layers of 41 nm thickness grown on Si substrates by plasma enhanced chemically vapor deposition. The compositions of the grown films were determined by X-ray photoelectron spectroscopy. 

A problem remains in the present result As already mentioned, the current efficiency of Hj for the particulate-Cu/p-Si(ordinary) electrode is much higher than that on a Cu electrode (Table 1), indicating that the reaction proceeds not only on the Cu particles but also on the naked Si part of the particulate-Cu/p-Si(ordinary) electrode. This effect should be much smaller on the particulate-Cu/p-Si(best) as is understood from Fig. 2, but it is not easy to obtain such an electrode reproducibly. To reduce the Hj evolution may be possible by suppressing the reaction on the naked Si part, e.g., by making a silicon oxide layer on it or by increasing the amount of Cu particles. 

As substrate for the sample preparation, silicon wafers from Wacker Chemie AG (Munich, Germany) with a natural silicon oxide layer (thickness 3.8 nm) and a surface roughness of 0.3 nm is used. The wafers are split into small pieces of about 1x1 cm. The pieces are cleaned in a bath sonicator for 20 min in CHCl they are dried in a atmosphere. 

Fig. 12 An electronic device based on a single rolled-up sheet of carbon atoms. (From Ref. () In the figure, a CNT (red about 1 nm in diameter) bridges two closely spaced (400 nm apart) platinum electrodes (labeled source and drain) atop a silicon surface coated with an insulating silicon oxide layer. Applying an electric field to the silicon (via a gate electrode, not shown) turns on and off the fiow of current across the nanotube, by controlling the movement of charge carriers onto the nanotube. (View this art in color at www.dekker.com.)...

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