Silicon device fabrication

Graff K (2000) Metal impurities in silicon device fabrication. Springer, Berlin... 

Fig. 10. Complete fabrication sequence for manufacturing a moderately complex silicon device, (a) Front end processing, and (b) assembly and test.

An important consideration in the sequence of semiconductor devices fabrication is the so-called thermal budget, a measure of both the CVD temperature and the time at that temperature for any given CVD operation. As a rule, the thermal budget becomes lower the farther away a given step is from the original surface of the silicon wafer. This restriction is the result of the temperature limitations of the already deposited materials. 

Daumengrofes Labor aus Aluminium-Folie, Blick durch die Wirtschafi, June 1997 Heterogeneous gas-phase micro reactor micro-fabrication of this device anodic oxidation of aluminum to porous catalyst support vision of complete small laboratory numbering-up development of new silicon device [225]. 

On the way to more reliability in device fabrication, Kronholz et al. reported on the reproducible fabrication of protected metal nanoelectrodes on silicon chips with <30nm gap width and their electrochemical characterization [33]. For the fabrication of the chips, an optical lithography step and two electron-beam steps are combined (Figure 18). 

It is important to note that the entire NW-TFT device fabrication process is performed essentially at room temperature. Therefore, the assembly of high-performance NW-TFTs can be readily applied to low-cost glass and plastic substrates. It has been demonstrated, for example, that NW-TFTs can be fabricated on plastic substrates (Fig. 11.14d) with carrier mobilities comparable with those made on silicon substrates. Moreover, studies demonstrate that... 

Unlike silicon-based materials where selective reactants are of ultimate importance, and III-V and metallic materials where product volatility dominates etching considerations, selective etching of organic films is driven by incorporating the desired reactivity (or lack of it) into the film itself. In device fabrication all types of materials are present simultaneously and the process engineer must be aware of the important aspects of the chemistry of each material in addition to the gas phase reactions that produce chemically active species. It is hoped that the discussions presented here provide a basis for approaching such a complex chemical system and for critically evaluating studies which appear in the literature. 

Surface layers of silicon oxide are important in semiconductor device fabrication as interlayer dielectrics for capacitors, isolation of conducting layers, or as masking materials. However, anodic oxides, due to their relatively poor electrical properties, breakdown voltage, and leakage current, have not yet found much use in device technology, and cannot compete with thermal oxides obtained at high temperatures of 700 to 900 °C. 

The increasing importance of multilevel interconnection systems and surface passivation in integrated circuit fabrication has stimulated interest in polyimide films for application in silicon device processing both as multilevel insulators and overcoat layers. The ability of polyimide films to planarize stepped device geometries, as well as their thermal and chemical inertness have been previously reported, as have various physical and electrical parameters related to circuit stability and reliability in use (1, 3). This paper focuses on three aspects of the electrical conductivity of polyimide (PI) films prepared from Hitachi and DuPont resins, indicating implications of each conductivity component for device reliability. The three forms of polyimide conductivity considered here are bulk electronic ionic, associated with intentional sodium contamination and surface or interface conductance. 

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