Shadowing masks

The minimum size of the monochrome pixels (we consider color in Section 13.7.3) that can be fabricated using OLEDs is dictated primarily by the ability to pattern the electrode which is deposited on top. OLEDs are not sufficiently robust to withstand the normal processes of photolithography. Among the schemes which have been suggested for high resolution patterning is one in which the substrate is pne-pattemed to provide its own shadow mask [1911. By this means, pixel sizes down to 300 p have been demonstrated, and a lower limit of about 100 p is estimated. 

Fig. 2 (a) Edwards E308 evaporator. One quartz-crystal thickness monitor is pointed towards the Au source to monitor Au vapor deposition on chamber walls the other monitors Au deposited through the shadow mask atop the organic layer. In the cold Au deposition, a small amount of Ar gas is added to the chamber to cool the Au atoms to room temperature before they physisorb atop the cryocooled organic monolayer, (b) Geometry of an Au I monolayer I Au pad sandwich, with electrical connections made using a Ga/In eutectic... 

Figure 4.8. Current voltage curves for selected A1PO capacitor structures. A high-quality thermally oxidized Si02 dielectric in an identical structure is included for reference. Top contacts are 0.011-cm2 A1 dots thermally evaporated via shadow mask. Bottom contact is made via conductive substrate p++ Si in the case of 600 °C A1PO and Si02 capacitors, and sputtered Ta metal for 300 °C A1PO devices.

Figure 4.10. Representative og(IB)-VGS behavior of an RF-sputtered ZTO-channel TFT on (a) 40-nm A1PO and (b) 100-nm Si02 gate dielectrics on unpatterned p++ Si gate electrodes. Channel and A1 S/D contacts were defined with shadow masks. Dielectric films were annealed at 600 °C prior to channel deposition, whereas the completed stack was annealed at 300 °C. 

FIGURE 7.3 Schematic representation of the basic steps required in fabricating a vapor-deposited OLED test pixel, (a) anode patterning via lithography, (b) deposition of the organic, and (c) metal cathode layers through shadow masks. 

The metal cathode is deposited onto the organic layers through a shadow mask (see Figure 7.3c). For active-matrix OLED (AMOLED) displays, a single unbroken cathode is often used over the entire display area. 

Each of the techniques described above has unique strengths and weaknesses, and the optimum device structure for commercial full-color displays will also be heavily influenced by the ease with which it can be mass-produced. Currently full-color OLED displays have been manufactured commercially by using two of the above described techniques only, i.e., (a) side-by-side pixels deposited by high-precision shadow masking and (b) using white OLEDs and color absorption filters. 

A shadow-mask technique has been applied for the local metal deposition to exclude metal residues on other designs processed on the same wafer (Fig. 4.2b). Such metal residues may be caused by imperfections in the patterned resist due to topographical features on the processed CMOS wafers or dust particles. The metal film is only deposited in those areas on the wafer, where it is needed for electrode coverage on the microhotplates. This also renders the lift-off process easier since no closed metal film is formed on the wafer, so that the acetone has a large surface to attack the photoresist. Another advantage of the local metal lift-off process is its full compatibility with the fabrication sequence of chemical sensors based on other transducer principles [20]. 

A silicon wafer with anisotropically KOH-etched openings was used as shadow mask. The shadow mask is accurately positioned with the help of an optical microscope and fixed using a custom-made wafer holder. A 50-nm-thick TiW-film is deposited by sputtering through the shadow mask. This film serves as adhesion layer and diffusion barrier and covers the rough surface of the CMOS-Al-metallization. A Pt-layer with a thickness of 100 nm was sputtered on top of this TiW-layer. 

CMOS CMOS CMOS backside shadow mask local nitride passivation metaiiizatipn oxjdes passivation nitride ------- ... 

Fig. 4.15. Silicon nitride spot locally deposited through a shadow mask on a bare Si-substrate...

In order to establish good electrical contact to the sensitive layer, it was necessary to coat the electrodes with a metal stack of Ti/W (diffusion barrier and adhesion layer) and Pt. The usage of a shadow mask during the metal deposition ensures full compatibility with other MEMS processing steps so that it is possible to fabricate various CMOS-MEMS devices on the same wafer. 

Schematic of the Si-nMEA fabrication process (a) sputter Au layer on double-side polished wafer (b) pattern Au layer with liftoff process (c) spincoat and cure a polyimide layer (d) perform the double-sided photolithography to pattern etch pits (e) etch Si in ICP-DRIE to form Au/Si electrode (f) dice the wafer into a single die (g) RIE etch the polyimide layer with a shadow mask to expose current collecting region (h) electroplate Pt black on Au layer (i) sandwich both electrodes with Nafion 112 in a hot-press bonder. (Reprinted from J. Yeom et al. Sensors Actuators B107 (2005) 882-891. With permission from Elsevier.)...

An already substantial and rapidly growing market for CRT phosphors and tubes is in the area of data displays, both alphanumeric and graphic, e.g., computer terminals and word processors. In spite of dramatic advances in other technologies, CRT s are still the most cost effective way to present information, and very likely always will be. Most data display tubes do not use rare earth phosphors because of their high cost, rare earth phosphors find use only when there is a compelling need for their special properties. At the present time, this is limited to the use of Eu3+ reds in tricolor tubes that use the same shadow mask principle as conventional color TV. 

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