Semiconductor processing, fabrication steps

The material properties of PS offer new ways of making electronic devices. For the manufacture of cold cathodes, for example, oxidized microporous polysilicon has been found to be a promising material. The application of basic semiconductor processing steps such as doping, oxidation and CVD to a macroporous material enable us to fabricate silicon-based capacitors of high specific capacitance. Both devices will be discussed below. 

Semiconductor Production Integrated circuits (ICs) are the major product of the semiconductor industry, and their production involves the use of hundreds of materials, products, and processes. Many different machines are used in the wafer fabrication step and these machines need to be cleaned periodically. Most machine cleaning is performed with CFC-113. 

The convincing advantage of surface micromachining is its similarity to classical IC fabrication, which is limited to the wafer surface as well. Both fabrication techniques and structures are therefore similar and well understood. Only a few specific processes had to be developed to supplement the established standard semiconductor processing steps. 

Step and Hash Imprint Lithography (SFBL, a trademark of Molecular Imprints, Inc.) is a low-temperature, low-pressure UV-NIL process targeted for applications in complementary metal oxide semiconductor (CMOS) fabrication [51]. In this process, a low-viscosity liquid monomer fills the space between the template and a substrate and is then exposed to UV irradiation, which initiates a polymerisation that vitrifies the imprint fluid. 

Conventional electronic devices are made on silicon wafers. The fabrication of a silicon MISFET starts with the diffusion (or implantation) of the source and drain, followed by the growing of the insulating layer, usually thermally grown silicon oxide, and ends with the deposition of the metal electrodes. In TFTs, the semiconductor is not a bulk material, but a thin film, so that the device presents an inverted architecture. It is built on an appropriate substrate and the deposition of the semiconductor constitutes the last step of the process. TFT structures can be divided into two families (Fig. 14-12). In coplanar devices, all layers are on the same side of the semiconductor. Conversely, in staggered structures gate and source-drain stand on opposing sides of the semiconductor layer. 

Polymer films that are sensitive to light, x-rays, or electrons— known as photoresists—are nsed extensively to transfer the pattern of an electronic circuit onto a semiconductor surface. Such films must adhere to the semiconductor surface, cross-link or decompose on exposure to radiation, and nndergo development in a solvent to achieve pattern definition. Virtually all aspects of photoresist processing involve surface and interfacial phenomena, and there are many outstanding problems where these phenomena mnst be controlled. For example, the fabrication of multilayer circuits requires that photoresist films of about 1-pm thickness be laid down over a semiconductor surface that has already been patterned in preceding steps. 

The TFT fabrication process on glass substrates starts with 100 nm of Cr for the gate metal, and is followed by a PECVD 200 nm thick Si3N4 dielectric with a 30 nm thick SiC>2 surface layer. The source drain metal is Cr/Au. Each of these layers is patterned using printed wax masks and chemical etching, steps a to d in Fig. 11.8. The surface is modified with a solution deposition of a self-assembled monolayer of octyltrichlorosilane (OTS-8) before inkjet printing deposition of the semiconductor. It has been shown that the OTS-8 layer affects the structural order of PQT-12 in thin films, improving the performance of the TFT [23]. Encapsulation and possibly other subsequent layers may be needed on the TFT, but these are not discussed here. 

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