Pin-grid array

Pin Grid Arrays. Standard chip carriers are limited to ICs with 124... 

Figure 6. Cofired ceramic pin grid array package with 270 pins and a tape-automated-bonded 1C.

Finally, when a circuit or component doesn t have to be removed often and it contains a large number of transistors, typically you use a PGA and a ZIP (Figure 1.9). PGA stands for Pin Grid Array, describing the array of pins used to connect the chip to the circuit board. ZIF stands for zero insertion force, which describes how easy it is to place a chip in this kind of socket. It is a type of socket that works with PGA chips to allow them to be mounted on a circuit board. 

Older CPUs are generally square, with transistors arranged in a Pin Grid Array (PGA). Prior to 1981, chips were found in a rectangle with two rows of 20 pins known as a Dual Inline Package (DIP). See Figure 2.20. There are still integrated circuits that use the DIP form factor. However, the DIP form factor isn t used for PC CPUs anymore. Most CPUs use either the PGA or the SECC form factor (discussed earlier). 

After the 808x series came the 80x86 series, otherwise known simply as Intel s x86 series. The 80286 was the first to implement the PGA (Pin Grid Array) as described earlier in this section. It ran hotter than the 8088, with speeds from 6MHz to 20MHz. Both internal and external bus structures were 16 bits wide, and it could physically address up to 16MB of RAM. 

PGA (Pin Grid Array) A type of IC package that consists of a grid of pins connected to a square, flat package. 

Figure 4 shows an example of a pin grid array (PGA), developed to accommodate IC s with 84 or more pins. The original PGA s were ceramic packages, but several techniques are now used to produce them in plastic. The PGA s can be through-hole mounted on the printed wiring board, or can be socketed and surface mounted. 

Figure 4. Pin grid array. (Reproduced with permission from Ref. 4. Copyright 1988 BPA [Technology and Management, Ltd.].)...

ICs, chip carriers, and packages may have their I/O connections formed throughout the surface area (area arrays) as opposed to peripheral I/Os as with wire-bond pads on die or axial leads on packages. Area arrays include flip-chip, BGA, and pin-grid arrays. Area-array devices provide very high I/O counts per surface area, which are necessary for increased functionality. 

Wong CP. Polymers for Electronic and Photonic Applications. Academic Press 1993. Tan N, Lim K, Chin B, Bourdillon A. Engineering surfaces in ceramic pin grid array... 

Tan N, Chin B, Lim KHK, Bourdillon AJ. Engineering surfaces in ceramic pin grid array packaging to inhibit epoxy bleeding. Hewlett Packard J. Aug. 1998. 

FIGURE 34.9 A ceramic pin-grid-array package (96% pure AijOs with multilayer Au metallization. 

Tan, N., Lim, K., Chin, B., and Bourdillon, A., Engineering Surfaces in Ceramic Pin Grid Array Packaging to Inhibit Epoxy Bleeding, Hewlett-Packard J. (Aug.1998)... 

Loctite 3561/ Loctite High-piirity liquid epoxy 1 Ceramics, laminates Automated dispensing Bare chip protection in chip on board, MCMs, BGAs, and pin-grid arrays. 

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