Memory chips vertically stacking

If the 2.5-D technology is available, it s possible to re-organize the RDRAM chip so that the signal path can be significantly reduced. Suppose we need to design a memory system composed of four RDRAM chips. In the conventional solution, the four chips will be serially connected as shown in Fig. 3.5. In a 2.5-D stacked memory system illustrated in Fig. 3.6, the DRAM cells can now be placed into four layers and vertically stacked. The memory bus will be through inter-chip contacts, which have only a vertical height of <50 pm. As a result, 2.5-D stacked Rambus DRAM has a considerable potential to achieve superior performance at a relatively low cost. 

In this approach, entire wafers or segments of wafers containing ICs are stacked. Interconnections are formed from vias in the silicon. In vertically stacking memory chips or other IC chips, the chips are first thinned to several mils (4 mils or less), then adhesive bonded, and electrically interconnected directly from chip-to-chip, either from the edges or through vias in the silicon. In these approaches, both electrically conductive and electrically insulative adhesives are used. Thermally conductive preform adhesives or thin thermoplastic films are used to bond and isolate the chips within the stack and to dissipate heat. Several processes are available to vertically stack and interconnect chips of the same size and function such as SRAM, flash, and DRAM memory chips. Other processes have been developed to vertically stack chips of different sizes and functions, or to horizontally interconnect different chips in one layer, then vertically stack the layers. ... 

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