Mask etching

FIGURE 2.3 Sequence for fabrication of the glass microfluidic chip, (a) Cr and Au masked glass plate coated with photoresist (b) sample exposed to UV light through a photomask (c) photoresist developed (d) exposed metal mask etched (e) exposed glass etched (f) resist and metal stripped (g) glass cover plate bonded to form sealed capillary [102]. Reprinted with permission from American Chemical Society. 

Structuring by Means of Masked Etching in Microsystems Technology... 

Mask, Etch, then Strip Mask CVD, Mask. Etch, Strip Mask CVD of Final Layer... 

Polymers can be etched by oxygen plasmas using silicon, metal, and oxide masks. Etch rates of a few pm/min have been demonstrated with 20 1 aspect ratios. A Bosch process for polymer etching involves an O2 etch step followed by a C4Fg passivation step. 

Doping. Electron-acceptor atoms such as boron or electron-donors such as phosphorus are introduced into the area exposed by the etch process to alter the electrical character of the pure silicon, which is an intrinsic semiconductor. These areas are called p-type (e.g., with boron) or n-type (e.g., with phosphorus) to reflect their particular charge carrier in the conduction process. Repeating the previous steps, i.e., thermal oxidation, masking, etching, and doping operations are repeated several times until the last front-end layer is completed, i.e., all active devices have been formed. 

Most IC failures, as for semiconductors, are related to manufacturing defects (Fig. 7.159 is the inside view of a typical acceptable IC). A breakdown of typical IC failure mechanisms is 40.7% wire bond interconnects, 23.4% misapphcation/misuse, 4.2% masking/etching defect, 3.3% die mechanical damage, 1.4% cracked die, 0.9% die metallization corrosion, 0.9% die contamination, and 24.8% other causes. 

Precap visual Slice preparation Passivation Masking Etching Metallizations Die separation Die bonding Wire bonding Increased leakage, low insulation breakdown, opens, shorts, intermittents, potential shorts or opens, high internal resistances, intermittent shorts... 

As discussed above, the patterning of a thin film layer usually involves deposition of the thin film followed by photolithography and masked etching. However, this may not be the most convenient method for some materials, especially some metals, considering factors such as etch type (wet or dry), availability of etchants, etch rates, masking materials, and selectivity. Lift-off is an alternative method to pattern such materials while avoiding the etching step. 

Figure 3.13 illustrates how a polycrystalline silicon cantilever beam is formed onto a Si substrate. We first deposit a layer of SiN onto the Si substrate as an insulator. Next, a layer of SiOj is deposited and patterned onto the substrate via LPCVD, followed by photolithography and masked etching of Si02 to expose the underlying SiN at a designated anchor area. Polycrystalline... 

Repeating the Steps - The thermal oxidation, masking, etching and doping steps are repeated several times until the last front end layer is completed (all active devices have been formed). 

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