Instruction decoder, processing

It can be seen from Fig. 4.2 that the trellis expand operation is called several times as we progress in the decoding process. Therefore, it is desirable to create a custom trellis expand instruction which executes this operation efficiently. We enhance the ISA of DLX processor and create the Texpand instruction in CPUSIM simulator in order to efficiently execute the trellis expand operation. The detailed architecture of DLX processor is described in the following sections. 

The instruction decoder is similar to ftie type of logic seen in both Chapters 4 and 7. The combinational logic that it contains will create a large circuit when synthesized but should be easy to optimize. However, this will rely on the structured design that the components and processes create by being flattened. Only in tfiis way can the optimizer minimize the duplication across the whole logic block. 

When the cell requires instructions for protein production, part of the code on DNA, starting at an initiator and ending at a stop codon, is converted into a more mobile form by transferring the DNA code into a matching RNA code on a messenger ribonucleic acid (mRNA), a process known as transcription. The decoding, or translation, of mRNA then takes place by special transfer ribonucleic acids (tRNA), which recognize individual codons as amino acids. The sequence of amino acids is assembled into a protein (see Proteins section). In summary, the codes on DNA... 

The CENTRAL PROCESSING UNIT (CPU) decodes and executes the instructions of a computer program. It has circuits that can perform arithmetic and logical operations, e.g., add two numbers or compare them for equality. 

The next step in forming pipestages is to place the SELECT stages into separate vtbodies, then transform each vtbody into a process and then a pipestage. First, Vtbody Formation is used to encapsulate each SELECT into a separate vtbody. As shown in Figure 8-14, this results in four vtbodies an IFETCH vtbody, which increments the PC a DECODE vtbody, which decodes the instruction and addressing mode an OPFETCH vtbody, which calculates the effective address and fetches the operand and an EXECUTE vtbody, which executes the instruction. 

The main architecture of the decoder is shown in Figure 8.21. CONTROL-BEHAVIOUR only processes the incoming 20-bit instruction when the MATCH and C (INSTR(I9)) bits indicate that it is destined for this PE. The first action is to enable the function required - read, write, multiply and so... 

INSTRUCTION process — decode the actual instruction begin... 

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