VHDL Gate Level Simulation

To perform gate level simulation of a VHDL netlist one requires the VHDL simulation libraries from the ASIC vendor. The Synopsys liban utility can generate the VHDL library models from the synthesis technology library. For tiie more complex cells, simulation models will have to be manually created. The VHDL models generated are encrypted so that the vendor proprietary information is protected. 

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You are performing gate level simulation. You have analyzed the VHDL gate level simulation models into a library. On invoking the simulator, you get a message that components are unbound. 

At the start of simulation, all the sequential elements on the ASIC including those in the TAP controller are uninitialized. Since the TAP controller does not have a reset pin (either synchronous or asynchronous) the "U"s keeps propagating to the data pin of the flops thereby not being able to move the TAP controller to the Idle state. One way is to arbitrarily initialize the state vector of the TAP controller to a known value at the start of simulation and then simulate your regular functional vectors. If you are using Synopsys VHDL System Simulator for your gate-level simulation, the VSS commands hold and assign can be used to clock a known arbitrary value into the TAP controller. 

Chapter 3 covers the simulation steps, i.e., both functional or behavioral simulation of the HDL and the post-sfynthesis or gate-level simulation. This chapter has been included, primarily, to help the reader understand the design flow better. An example VHDL code of TAP controller is provided along with its testbench. The steps to perform behavioral simulation, and gate level simulation after synthesis have been discussed. The simulator used here is the Synopsys VHDL System Simulator (VSS). However, discussion on VSS is beyond the scope of this book. 

The type buffer can be used when an output must be used internally. The use of mode buffer is not recommended for synthesis. This is because ports of mode buffer can only be associated with ports of mode buffer and gate level VHDL simulation models from ASIC vendors never use the mode buffer. Once declared as a buffer, all... 

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