Gate Insulator Thickness

According to the interference condition for the optical path difference the film thiekness, d, can be estimated by 

---

FIG. 6.18. Output characteristics for BC pentacene TFTs with (a) Au-Pd and (b) Ni-Pd contacts. All TFTs had dimensions of L = 10 pm, W = 220 pm, and Si02 gate insulator thickness of 290 nm. The dashed lines correspond to the devices biased with the Pd contact as the source [163]. 

Figure 4. Potential profile of a Z, = 1.5/tm a-6T FET for Kds = -lOOV and Kgs = -80 V. The gate insulator thickness is 300 nm. Reprinted with permission from Ref. 23. Copyright 1997 IEEE.

Figure 5. Current-voltage characteristics of an o -6T FET with L= 1.5 pm and gate insulator thickness 300 nm. Reprinted with permission from Ref. 20. Copyright 1995 American Institute of Physics.

Fig. 6 Simulated output characteristics for Vgs = — lOV (a) and transfer characteristics for the given drain voltages (b) for the two channel length 0.5 pm (open symbols) and 0.3 pm (filled symbols). The gate insulator thickness is varied as indicated. Further parameters p-doping lO cm oftheSOnm P3HT layer, mobility p = 10 cm V s . Figure 6 a taken from [15]...

The thickness dependence of mobility in CuPc-based OFETs on amorphous Si02 substrate was investigated by Gao et al. in 2007 [66], The results demonstrated that the mobility increased with increasing the thickness of CuPc layer and then was saturated at the thickness of 7.8 nm with mobility about 0.008 cm2 V-1 s-1. In 2008, Du and co-workers fabricated CuPc-based OFETs using PMMA and P(MMA-co-GMA) as gate insulators, and the difference between devices with different polymer gate insulators were explained with XRD, AFM, and SEM measuring... 

FET characteristics published by a number of laboratories engaged in this development. In Fig. 6 some of the most recent results are shown. We follow Powell et al. (1981) in plotting the sheet conductance Gs against the field at the insulator/a-Si H interface in order to allow for different device geometries and gate dielectrics. The interface field has been calculated from VG/esid, where and ea are the relative permittivities of the gate insulator and of the a-Si H, respectively, and d is the thickness of the gate insulator. The curve denoted by D represents the data described in this paper. Curve P is from Powell et al. (1981) at the Philips Research Laboratories the curves marked T are from data published by Matsumura et al. (1981) and Hayama and Matsumura (1981) and curves C and F represent recent results from the Canon (Okubo et al., 1982) and Fujitsu (Kawai et al., 1982) laboratories, also in Japan. 

Fig. 2. Schematic illustration of the ZnO based TFT structure. The ZnO chaimel layer and the ATO gate insulator are 100 run and 220 run in thickness, respectively, while the ITO gate and the GZO source and drain are 200 run and 150 run in thickness, respectively. The channel length and gate width ratio varied between 1 and 65.

Figure 25.3 Scheme of the three major steps of FET fabrication. After preparing source drain contacts by Ag paste (a) the gate insulator is fabricated by a two-step temperature process of para-cyclophane (b). Finally, by thermal evaporation of Au the top-gate contact of 20 nm thickness is deposited (c). An image of the resulting structure is shown in (d) for a DIP crystal FET. 

The silicon dioxide gate insulator is 30 nm thick. This short channel has been prepared without high resolution lithography by using undercutting for the definition of the sub-micrometer channel length. 

---