Drain leakage current

Drain leakage current when the transistor is off. That is, the gate voltage Vqs biases the device below the subthreshold region. This current is often called the off-current. 

The MOSEET has three regions of operation. The cutoff region occurs for V g < Up. In this region, the drain-to-source current is the reverse saturation current of the back-to-back source and drain junctions. This leakage current is small but nonzero and allows charge to leak off capacitors which are isolated by cutoff MOSFETs. Because this is how bits are stored in dynamic memory (DRAM) ceUs, DRAMs must be regularly refreshed to retain their memory. 

The inkjet-printed (or inkjetted ) TFT operated with a mobility of 6.5cm2/ Vs and an on/off ratio of three digits as shown in Fig. 5.6b. This low mobility is attributed to the poor crystallinity and rough surface, whereas the large off current, which was confirmed to be the current between source and drain rather than a leakage current through the gate insulator, is also attributed to... 

It is noteworthy, that, in the case of the MOSFET heater, the transistor temperature is a function of the drain current, and, therefore, the leakage current also strongly depends on the drain current. As it is shown in Fig. 4.21 the leakage current amounts... 

Fig. 4.21. Ratio of the leakage current of the reverse-biased drain/n-weU junction and the drain current as a function of the drain current. A drain current of 14 niA corresponds to a membrane temperature of 375 °C...

CuPc thin films, and the enhanced physical connection between source-drain electrodes and semiconductor channel associated with the PMMA polymer layer, the OFET performance of this bottom-contact device was significantly improved with leakage current being reduced by roughly one order of magnitude and on-state current enhanced by almost one order of magnitude. The hole mobility of this bottom-contact OFET device reached 0.01 cm2 V-1 s 1, which is comparable with that of top-contact device but much higher than that of normal bottom-contact device without polymer layer [45],... 

Kawase et al. [17] fabricated All-polymer thin film transistors by inkjet printing technique. They used these transistors as active-matrix backplane for information displays. This field has been dominated by amorphous Si TFTs and large liquid crystal displays with an amorphous Si TFT active matrix backplane have been manufactured at a reasonable cost. An organic TFT is expected to reduce the cost even more, and to be applied to flexible displays based on a plastic substrate. The TFT characteristics required for active-matrix displays are (1) sufficient drain cmrent, (2) low off current, (3) low gate leakage current through an insulator, (4) small gate overlap capacitance and (5) uniform characteristics. 

Figure 8.7 (a) Drain-current (/p)-drain-voltage (Fd) characteristics of sample A measured at room temperature, (b) /n-Fn curves from (a) corrected for leakage currents across the gate insulator, (c) as (b), but corrected for ohmic currents in addition. The lines in (c) represent simulated... 

In the fabrication of OTFT backplanes there are complications related to the order in which the organic semiconductor and source/drain contacts are deposited and how they are patterned. The semiconductor must be patterned in order to avoid large leakage currents through the ungated areas. Complications arise because the... 

The depletion mode 6H-SiC MOSFETs fabricated by the General Electric group [8] exhibited a fairly low leakage current of 5 x 10 " A at 23 °C at -10 V gate bias and drain bias of 8 V with the on-current as high as 1.6 mA. However, the subthreshold was quite low. These devices operated up to 350 °C. 

Fig. 5.9. (a) A true Corbino, and (b) two partially shielded drain structures. While the Corbino architecture requires an additional metal layer to feed the drain electrode into the center without shorting the gate, it eliminates the need to pattern the semiconductor due to the source, which shields stray leakage currents. The partially shielded structures are a compromise between the lateral structure and a full Corbino architecture. The performance achieved depends on the layout details of the circuit in question and the ungated sheet resistance of the semiconductor. 

---